Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	475911667	8174834	0	0
check_regwen_rd_A	475911667	3671	0	0
check_timeout_rd_A	475911667	3309	0	0
check_trigger_regwen_rd_A	475911667	3426	0	0
consistency_check_period_rd_A	475911667	3773	0	0
creator_sw_cfg_read_lock_rd_A	475911667	3509	0	0
direct_access_address_rd_A	475911667	3153	0	0
direct_access_wdata_0_rd_A	475911667	1613	0	0
direct_access_wdata_1_rd_A	475911667	2213	0	0
integrity_check_period_rd_A	475911667	3641	0	0
intr_enable_rd_A	475911667	4367	0	0
owner_sw_cfg_read_lock_rd_A	475911667	3321	0	0
rot_creator_auth_codesign_read_lock_rd_A	475911667	3637	0	0
rot_creator_auth_state_read_lock_rd_A	475911667	3118	0	0
vendor_test_read_lock_rd_A	475911667	3112	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	8174834	0	0
T4	584642	97355	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T13	0	166107	0	0
T14	0	185737	0	0
T16	0	41986	0	0
T17	0	65799	0	0
T18	0	68950	0	0
T19	0	220130	0	0
T20	0	28733	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T135	0	68524	0	0
T136	0	62748	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3671	0	0
T4	584642	142	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	318	0	0
T20	0	72	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	71	0	0
T323	0	75	0	0
T338	0	82	0	0
T339	0	66	0	0
T340	0	138	0	0
T341	0	93	0	0
T342	0	82	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3309	0	0
T4	584642	137	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	289	0	0
T20	0	25	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	102	0	0
T323	0	61	0	0
T338	0	95	0	0
T339	0	66	0	0
T340	0	134	0	0
T341	0	73	0	0
T342	0	135	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3426	0	0
T4	584642	66	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	201	0	0
T20	0	58	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	94	0	0
T323	0	67	0	0
T338	0	120	0	0
T339	0	72	0	0
T340	0	73	0	0
T341	0	98	0	0
T342	0	101	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3773	0	0
T4	584642	135	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	243	0	0
T20	0	61	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	137	0	0
T323	0	65	0	0
T338	0	94	0	0
T339	0	84	0	0
T340	0	97	0	0
T341	0	99	0	0
T342	0	93	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3509	0	0
T4	584642	85	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	232	0	0
T20	0	44	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	119	0	0
T323	0	121	0	0
T338	0	113	0	0
T339	0	66	0	0
T340	0	119	0	0
T341	0	95	0	0
T342	0	111	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3153	0	0
T4	584642	89	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	285	0	0
T20	0	30	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	117	0	0
T323	0	97	0	0
T338	0	97	0	0
T339	0	53	0	0
T340	0	133	0	0
T341	0	154	0	0
T342	0	166	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	1613	0	0
T4	584642	88	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	202	0	0
T20	0	42	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	84	0	0
T323	0	57	0	0
T338	0	53	0	0
T339	0	4	0	0
T340	0	64	0	0
T341	0	38	0	0
T342	0	87	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	2213	0	0
T4	584642	64	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	241	0	0
T20	0	10	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	89	0	0
T323	0	61	0	0
T338	0	95	0	0
T339	0	54	0	0
T340	0	98	0	0
T341	0	78	0	0
T342	0	86	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3641	0	0
T4	584642	88	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	257	0	0
T20	0	38	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	97	0	0
T323	0	84	0	0
T338	0	118	0	0
T339	0	66	0	0
T340	0	78	0	0
T341	0	94	0	0
T342	0	133	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	4367	0	0
T4	584642	90	0	0
T5	22643	0	0	0
T7	0	4	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	269	0	0
T20	0	57	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T115	0	61	0	0
T237	0	38	0	0
T318	0	95	0	0
T323	0	113	0	0
T338	0	79	0	0
T339	0	66	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3321	0	0
T4	584642	101	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	268	0	0
T20	0	46	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	91	0	0
T323	0	92	0	0
T338	0	109	0	0
T339	0	53	0	0
T340	0	107	0	0
T341	0	100	0	0
T342	0	122	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3637	0	0
T4	584642	140	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	325	0	0
T20	0	58	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	110	0	0
T323	0	85	0	0
T338	0	121	0	0
T339	0	120	0	0
T340	0	91	0	0
T341	0	62	0	0
T342	0	123	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3118	0	0
T4	584642	80	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	199	0	0
T20	0	41	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	85	0	0
T323	0	66	0	0
T338	0	66	0	0
T339	0	74	0	0
T340	0	152	0	0
T341	0	93	0	0
T342	0	95	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	3112	0	0
T4	584642	98	0	0
T5	22643	0	0	0
T10	9672	0	0	0
T11	10312	0	0	0
T12	75949	0	0	0
T19	0	202	0	0
T20	0	51	0	0
T27	98077	0	0	0
T69	11024	0	0	0
T76	13866	0	0	0
T100	150233	0	0	0
T101	147987	0	0	0
T318	0	85	0	0
T323	0	86	0	0
T338	0	112	0	0
T339	0	51	0	0
T340	0	112	0	0
T341	0	161	0	0
T342	0	107	0	0