Unified Coverage Report :: Module :: otp_ctrl_core_reg_top

Module : otp_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.53	100.00	94.11			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	98.53	100.00	94.11			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.53	100.00	94.11			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	99.65	95.87	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_check_error	100.00	100.00
u_alert_test_fatal_macro_error	100.00	100.00
u_alert_test_fatal_prim_otp_alert	100.00	100.00
u_alert_test_recov_prim_otp_alert	100.00	100.00
u_check_regwen	100.00	100.00	100.00			100.00
u_check_timeout	100.00	100.00	100.00			100.00
u_check_trigger_consistency	100.00	100.00
u_check_trigger_integrity	100.00	100.00
u_check_trigger_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_consistency_check_period	100.00	100.00	100.00			100.00
u_creator_sw_cfg_digest_0	100.00	100.00
u_creator_sw_cfg_digest_1	100.00	100.00
u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_direct_access_address	100.00	100.00	100.00			100.00
u_direct_access_cmd_digest	100.00	100.00
u_direct_access_cmd_rd	100.00	100.00
u_direct_access_cmd_wr	100.00	100.00
u_direct_access_rdata_0	100.00	100.00
u_direct_access_rdata_1	100.00	100.00
u_direct_access_regwen	100.00	100.00
u_direct_access_wdata_0	100.00	100.00	100.00			100.00
u_direct_access_wdata_1	100.00	100.00	100.00			100.00
u_err_code_0	100.00	100.00
u_err_code_1	100.00	100.00
u_err_code_10	100.00	100.00
u_err_code_11	100.00	100.00
u_err_code_12	100.00	100.00
u_err_code_2	100.00	100.00
u_err_code_3	100.00	100.00
u_err_code_4	100.00	100.00
u_err_code_5	100.00	100.00
u_err_code_6	100.00	100.00
u_err_code_7	100.00	100.00
u_err_code_8	100.00	100.00
u_err_code_9	100.00	100.00
u_hw_cfg0_digest_0	100.00	100.00
u_hw_cfg0_digest_1	100.00	100.00
u_hw_cfg1_digest_0	100.00	100.00
u_hw_cfg1_digest_1	100.00	100.00
u_integrity_check_period	100.00	100.00	100.00			100.00
u_intr_enable_otp_error	100.00	100.00	100.00			100.00
u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_state_otp_error	100.00	100.00	100.00			100.00
u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_test_otp_error	100.00	100.00
u_intr_test_otp_operation_done	100.00	100.00
u_owner_sw_cfg_digest_0	100.00	100.00
u_owner_sw_cfg_digest_1	100.00	100.00
u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rot_creator_auth_codesign_digest_0	100.00	100.00
u_rot_creator_auth_codesign_digest_1	100.00	100.00
u_rot_creator_auth_codesign_read_lock	100.00	100.00	100.00			100.00
u_rot_creator_auth_state_digest_0	100.00	100.00
u_rot_creator_auth_state_digest_1	100.00	100.00
u_rot_creator_auth_state_read_lock	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_secret0_digest_0	100.00	100.00
u_secret0_digest_1	100.00	100.00
u_secret1_digest_0	100.00	100.00
u_secret1_digest_1	100.00	100.00
u_secret2_digest_0	100.00	100.00
u_secret2_digest_1	100.00	100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_check_pending	100.00	100.00
u_status_creator_sw_cfg_error	100.00	100.00
u_status_dai_error	100.00	100.00
u_status_dai_idle	100.00	100.00
u_status_hw_cfg0_error	100.00	100.00
u_status_hw_cfg1_error	100.00	100.00
u_status_key_deriv_fsm_error	100.00	100.00
u_status_lci_error	100.00	100.00
u_status_lfsr_fsm_error	100.00	100.00
u_status_life_cycle_error	100.00	100.00
u_status_owner_sw_cfg_error	100.00	100.00
u_status_rot_creator_auth_codesign_error	100.00	100.00
u_status_rot_creator_auth_state_error	100.00	100.00
u_status_scrambling_fsm_error	100.00	100.00
u_status_secret0_error	100.00	100.00
u_status_secret1_error	100.00	100.00
u_status_secret2_error	100.00	100.00
u_status_timeout_error	100.00	100.00
u_status_vendor_test_error	100.00	100.00
u_vendor_test_digest_0	100.00	100.00
u_vendor_test_digest_1	100.00	100.00
u_vendor_test_read_lock	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		337	337	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	1095	1	1	100.00
CONT_ASSIGN	1109	1	1	100.00
CONT_ASSIGN	1115	1	1	100.00
CONT_ASSIGN	1118	1	1	100.00
CONT_ASSIGN	1133	1	1	100.00
CONT_ASSIGN	1149	1	1	100.00
CONT_ASSIGN	1165	1	1	100.00
CONT_ASSIGN	1171	1	1	100.00
CONT_ASSIGN	1203	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1362	1	1	100.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1458	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1520	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1582	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
ALWAYS	1986	57	57	100.00
CONT_ASSIGN	2045	1	1	100.00
ALWAYS	2049	1	1	100.00
CONT_ASSIGN	2109	1	1	100.00
CONT_ASSIGN	2111	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2119	1	1	100.00
CONT_ASSIGN	2121	1	1	100.00
CONT_ASSIGN	2123	1	1	100.00
CONT_ASSIGN	2124	1	1	100.00
CONT_ASSIGN	2126	1	1	100.00
CONT_ASSIGN	2128	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2132	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2135	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2138	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2141	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2143	1	1	100.00
CONT_ASSIGN	2144	1	1	100.00
CONT_ASSIGN	2145	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2147	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2150	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2153	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2159	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2162	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2165	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2168	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2170	1	1	100.00
CONT_ASSIGN	2171	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2174	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2182	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2187	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2190	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2193	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2196	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2199	1	1	100.00
CONT_ASSIGN	2200	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2203	1	1	100.00
CONT_ASSIGN	2205	1	1	100.00
CONT_ASSIGN	2206	1	1	100.00
CONT_ASSIGN	2207	1	1	100.00
CONT_ASSIGN	2208	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2210	1	1	100.00
CONT_ASSIGN	2211	1	1	100.00
CONT_ASSIGN	2212	1	1	100.00
CONT_ASSIGN	2213	1	1	100.00
CONT_ASSIGN	2214	1	1	100.00
CONT_ASSIGN	2215	1	1	100.00
CONT_ASSIGN	2216	1	1	100.00
CONT_ASSIGN	2217	1	1	100.00
CONT_ASSIGN	2218	1	1	100.00
CONT_ASSIGN	2219	1	1	100.00
CONT_ASSIGN	2220	1	1	100.00
CONT_ASSIGN	2221	1	1	100.00
CONT_ASSIGN	2222	1	1	100.00
CONT_ASSIGN	2223	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	2225	1	1	100.00
ALWAYS	2229	57	57	100.00
ALWAYS	2290	87	87	100.00
CONT_ASSIGN	2556	0	0
CONT_ASSIGN	2564	1	1	100.00
CONT_ASSIGN	2565	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
450	1	1
465	1	1
481	1	1
487	1	1
502	1	1
518	1	1
534	1	1
550	1	1
566	1	1
1095	1	1
1109	1	1
1115	1	1
1118	1	1
1133	1	1
1149	1	1
1165	1	1
1171	1	1
1203	1	1
1235	1	1
1328	1	1
1331	1	1
1346	1	1
1362	1	1
1396	1	1
1427	1	1
1458	1	1
1489	1	1
1520	1	1
1551	1	1
1582	1	1
1614	1	1
1986	1	1
1987	1	1
1988	1	1
1989	1	1
1990	1	1
1991	1	1
1992	1	1
1993	1	1
1994	1	1
1995	1	1
1996	1	1
1997	1	1
1998	1	1
1999	1	1
2000	1	1
2001	1	1
2002	1	1
2003	1	1
2004	1	1
2005	1	1
2006	1	1
2007	1	1
2008	1	1
2009	1	1
2010	1	1
2011	1	1
2012	1	1
2013	1	1
2014	1	1
2015	1	1
2016	1	1
2017	1	1
2018	1	1
2019	1	1
2020	1	1
2021	1	1
2022	1	1
2023	1	1
2024	1	1
2025	1	1
2026	1	1
2027	1	1
2028	1	1
2029	1	1
2030	1	1
2031	1	1
2032	1	1
2033	1	1
2034	1	1
2035	1	1
2036	1	1
2037	1	1
2038	1	1
2039	1	1
2040	1	1
2041	1	1
2042	1	1
2045	1	1
2049	1	1
2109	1	1
2111	1	1
2113	1	1
2114	1	1
2116	1	1
2118	1	1
2119	1	1
2121	1	1
2123	1	1
2124	1	1
2126	1	1
2128	1	1
2130	1	1
2132	1	1
2134	1	1
2135	1	1
2136	1	1
2137	1	1
2138	1	1
2139	1	1
2140	1	1
2141	1	1
2142	1	1
2143	1	1
2144	1	1
2145	1	1
2146	1	1
2147	1	1
2148	1	1
2149	1	1
2150	1	1
2152	1	1
2153	1	1
2155	1	1
2157	1	1
2159	1	1
2160	1	1
2162	1	1
2163	1	1
2165	1	1
2166	1	1
2168	1	1
2169	1	1
2170	1	1
2171	1	1
2173	1	1
2174	1	1
2176	1	1
2178	1	1
2179	1	1
2181	1	1
2182	1	1
2184	1	1
2185	1	1
2187	1	1
2188	1	1
2190	1	1
2191	1	1
2193	1	1
2194	1	1
2196	1	1
2197	1	1
2199	1	1
2200	1	1
2202	1	1
2203	1	1
2205	1	1
2206	1	1
2207	1	1
2208	1	1
2209	1	1
2210	1	1
2211	1	1
2212	1	1
2213	1	1
2214	1	1
2215	1	1
2216	1	1
2217	1	1
2218	1	1
2219	1	1
2220	1	1
2221	1	1
2222	1	1
2223	1	1
2224	1	1
2225	1	1
2229	1	1
2230	1	1
2231	1	1
2232	1	1
2233	1	1
2234	1	1
2235	1	1
2236	1	1
2237	1	1
2238	1	1
2239	1	1
2240	1	1
2241	1	1
2242	1	1
2243	1	1
2244	1	1
2245	1	1
2246	1	1
2247	1	1
2248	1	1
2249	1	1
2250	1	1
2251	1	1
2252	1	1
2253	1	1
2254	1	1
2255	1	1
2256	1	1
2257	1	1
2258	1	1
2259	1	1
2260	1	1
2261	1	1
2262	1	1
2263	1	1
2264	1	1
2265	1	1
2266	1	1
2267	1	1
2268	1	1
2269	1	1
2270	1	1
2271	1	1
2272	1	1
2273	1	1
2274	1	1
2275	1	1
2276	1	1
2277	1	1
2278	1	1
2279	1	1
2280	1	1
2281	1	1
2282	1	1
2283	1	1
2284	1	1
2285	1	1
2290	1	1
2291	1	1
2293	1	1
2294	1	1
2298	1	1
2299	1	1
2303	1	1
2304	1	1
2308	1	1
2309	1	1
2310	1	1
2311	1	1
2312	1	1
2316	1	1
2317	1	1
2318	1	1
2319	1	1
2320	1	1
2321	1	1
2322	1	1
2323	1	1
2324	1	1
2325	1	1
2326	1	1
2327	1	1
2328	1	1
2329	1	1
2330	1	1
2331	1	1
2332	1	1
2333	1	1
2334	1	1
2335	1	1
2339	1	1
2343	1	1
2347	1	1
2351	1	1
2355	1	1
2359	1	1
2363	1	1
2367	1	1
2371	1	1
2375	1	1
2379	1	1
2383	1	1
2387	1	1
2391	1	1
2395	1	1
2396	1	1
2397	1	1
2401	1	1
2405	1	1
2409	1	1
2413	1	1
2417	1	1
2421	1	1
2425	1	1
2426	1	1
2430	1	1
2434	1	1
2438	1	1
2442	1	1
2446	1	1
2450	1	1
2454	1	1
2458	1	1
2462	1	1
2466	1	1
2470	1	1
2474	1	1
2478	1	1
2482	1	1
2486	1	1
2490	1	1
2494	1	1
2498	1	1
2502	1	1
2506	1	1
2510	1	1
2514	1	1
2518	1	1
2522	1	1
2526	1	1
2530	1	1
2534	1	1
2538	1	1
2542	1	1
2556		unreachable
2564	1	1
2565	1	1

---

Cond Coverage for Module : otp_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	628	591	94.11
Logical	628	591	94.11
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-2109	100.00
2114-2225	83.48

---

Branch Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		66	66	100.00
TERNARY	2045	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	2291	57	57	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2045	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T274,T275,T276
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2291	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T3,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T3,T8
addr_hit[30]	Covered	T1,T3,T8
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	475911667	9321458	0	0
reAfterRv	475911667	9321458	0	0
rePulse	475911667	7407476	0	0
wePulse	475911667	1913982	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	9321458	0	0
T1	21452	1899	0	0
T2	22056	1014	0	0
T3	19722	1818	0	0
T4	584642	36949	0	0
T5	22643	917	0	0
T8	11592	1962	0	0
T9	5578	61	0	0
T10	9672	336	0	0
T11	10312	1311	0	0
T12	75949	11826	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	9321458	0	0
T1	21452	1899	0	0
T2	22056	1014	0	0
T3	19722	1818	0	0
T4	584642	36949	0	0
T5	22643	917	0	0
T8	11592	1962	0	0
T9	5578	61	0	0
T10	9672	336	0	0
T11	10312	1311	0	0
T12	75949	11826	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	7407476	0	0
T1	21452	1679	0	0
T2	22056	934	0	0
T3	19722	1479	0	0
T4	584642	25372	0	0
T5	22643	836	0	0
T8	11592	1843	0	0
T9	5578	1	0	0
T10	9672	271	0	0
T11	10312	1002	0	0
T12	75949	10842	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	475911667	1913982	0	0
T1	21452	220	0	0
T2	22056	80	0	0
T3	19722	339	0	0
T4	584642	11577	0	0
T5	22643	81	0	0
T8	11592	119	0	0
T9	5578	60	0	0
T10	9672	65	0	0
T11	10312	309	0	0
T12	75949	984	0	0