Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24200632

1

T1

1554

T2

766

T3

8301

full_word

8022348

1

T1

966

T2

201

T3

4744

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32222680	1			T1	2520		T2	967		T3	13045
auto[TlIntgErrCmd]	97	1			T245	9		T246	5		T247	2
auto[TlIntgErrData]	102	1			T245	7		T246	9		T247	4
auto[TlIntgErrBoth]	101	1			T245	4		T246	6		T247	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9196275

1

T1

2244

T2

747

T3

11949

auto[1]

23026705

1

T1

276

T2

220

T3

1096

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5741278	1			T1	1405		T2	635		T3	7578
auto[TlIntgErrNone]	partial	auto[1]	18459078	1			T1	149		T2	131		T3	723
auto[TlIntgErrNone]	full_word	auto[0]	3454861	1			T1	839		T2	112		T3	4371
auto[TlIntgErrNone]	full_word	auto[1]	4567463	1			T1	127		T2	89		T3	373
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T245	4		T246	2		T247	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T245	5		T246	3		T247	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T335	1		T334	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T329	2		T334	2		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T245	3		T246	6		T247	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T245	4		T246	2		T247	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T329	2		T336	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T246	1		T337	2		T338	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T245	1		T246	2		T247	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T245	3		T246	4		T247	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T339	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T335	1		T340	2		T339	1