Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.93	98.05	96.15	96.85		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	459385081	7831697	0	0
check_regwen_rd_A	459385081	4186	0	0
check_timeout_rd_A	459385081	3013	0	0
check_trigger_regwen_rd_A	459385081	4318	0	0
consistency_check_period_rd_A	459385081	4592	0	0
creator_sw_cfg_read_lock_rd_A	459385081	3057	0	0
direct_access_address_rd_A	459385081	2409	0	0
direct_access_wdata_0_rd_A	459385081	1634	0	0
direct_access_wdata_1_rd_A	459385081	2037	0	0
integrity_check_period_rd_A	459385081	3929	0	0
intr_enable_rd_A	459385081	4913	0	0
owner_sw_cfg_read_lock_rd_A	459385081	2739	0	0
rot_creator_auth_codesign_read_lock_rd_A	459385081	3090	0	0
rot_creator_auth_state_read_lock_rd_A	459385081	2725	0	0
vendor_test_read_lock_rd_A	459385081	2788	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	7831697	0	0
T6	131984	299708	0	0
T12	131643	34913	0	0
T13	0	169796	0	0
T15	0	132517	0	0
T16	0	143666	0	0
T50	130947	0	0	0
T94	64818	0	0	0
T105	9806	0	0	0
T107	27058	0	0	0
T123	0	38500	0	0
T135	0	66069	0	0
T137	0	47370	0	0
T167	11117	0	0	0
T177	9968	0	0	0
T190	10723	0	0	0
T191	20836	0	0	0
T217	0	68420	0	0
T254	0	120410	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	4186	0	0
T15	706899	156	0	0
T17	0	136	0	0
T19	0	155	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	45	0	0
T258	0	84	0	0
T307	0	90	0	0
T308	0	132	0	0
T309	0	70	0	0
T310	0	61	0	0
T311	0	80	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	3013	0	0
T15	706899	244	0	0
T17	0	145	0	0
T19	0	161	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	35	0	0
T258	0	77	0	0
T307	0	88	0	0
T308	0	136	0	0
T309	0	197	0	0
T310	0	70	0	0
T311	0	80	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	4318	0	0
T15	706899	199	0	0
T17	0	206	0	0
T19	0	159	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	43	0	0
T258	0	55	0	0
T307	0	94	0	0
T308	0	138	0	0
T309	0	96	0	0
T310	0	63	0	0
T311	0	73	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	4592	0	0
T15	706899	215	0	0
T17	0	205	0	0
T19	0	209	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	66	0	0
T258	0	88	0	0
T307	0	122	0	0
T308	0	228	0	0
T309	0	145	0	0
T310	0	96	0	0
T311	0	93	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	3057	0	0
T15	706899	204	0	0
T17	0	182	0	0
T19	0	243	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	52	0	0
T258	0	125	0	0
T307	0	97	0	0
T308	0	183	0	0
T309	0	125	0	0
T310	0	60	0	0
T311	0	78	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	2409	0	0
T15	706899	199	0	0
T17	0	165	0	0
T19	0	162	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	65	0	0
T258	0	57	0	0
T307	0	171	0	0
T308	0	116	0	0
T309	0	168	0	0
T310	0	54	0	0
T311	0	73	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	1634	0	0
T15	706899	128	0	0
T17	0	123	0	0
T19	0	116	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	26	0	0
T258	0	67	0	0
T307	0	80	0	0
T308	0	133	0	0
T309	0	78	0	0
T310	0	45	0	0
T311	0	46	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	2037	0	0
T15	706899	133	0	0
T17	0	159	0	0
T19	0	166	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	29	0	0
T258	0	89	0	0
T307	0	80	0	0
T308	0	108	0	0
T309	0	79	0	0
T310	0	51	0	0
T311	0	55	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	3929	0	0
T15	706899	161	0	0
T17	0	165	0	0
T19	0	200	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	63	0	0
T258	0	57	0	0
T307	0	82	0	0
T308	0	170	0	0
T309	0	97	0	0
T310	0	40	0	0
T311	0	82	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	4913	0	0
T8	100548	15	0	0
T9	13964	0	0	0
T10	10457	0	0	0
T11	4768	0	0	0
T14	15650	0	0	0
T15	0	176	0	0
T17	0	208	0	0
T19	0	244	0	0
T96	0	54	0	0
T100	114855	0	0	0
T103	10155	0	0	0
T104	28733	0	0	0
T110	11842	0	0	0
T164	18019	0	0	0
T239	0	39	0	0
T307	0	133	0	0
T315	0	17	0	0
T316	0	1	0	0
T317	0	11	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	2739	0	0
T15	706899	91	0	0
T17	0	168	0	0
T19	0	168	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	50	0	0
T258	0	118	0	0
T307	0	105	0	0
T308	0	141	0	0
T309	0	116	0	0
T310	0	65	0	0
T311	0	53	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	3090	0	0
T15	706899	184	0	0
T17	0	173	0	0
T19	0	162	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	72	0	0
T258	0	66	0	0
T307	0	131	0	0
T308	0	192	0	0
T309	0	140	0	0
T310	0	76	0	0
T311	0	84	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	2725	0	0
T15	706899	147	0	0
T17	0	152	0	0
T19	0	160	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	53	0	0
T258	0	102	0	0
T307	0	84	0	0
T308	0	130	0	0
T309	0	129	0	0
T310	0	59	0	0
T311	0	40	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459385081	2788	0	0
T15	706899	152	0	0
T17	0	169	0	0
T19	0	128	0	0
T75	65374	0	0	0
T168	47940	0	0	0
T204	13271	0	0	0
T216	3739	0	0	0
T217	341109	0	0	0
T237	10844	0	0	0
T239	0	37	0	0
T258	0	104	0	0
T307	0	103	0	0
T308	0	156	0	0
T309	0	135	0	0
T310	0	66	0	0
T311	0	81	0	0
T312	36538	0	0	0
T313	32965	0	0	0
T314	34889	0	0	0