Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22996603

1

T1

835

T2

185550

T3

717

full_word

7713747

1

T1

213

T2

60680

T3

99

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30710050	1			T1	1048		T2	246230		T3	816
auto[TlIntgErrCmd]	106	1			T263	6		T264	4		T343	3
auto[TlIntgErrData]	105	1			T262	7		T263	10		T264	11
auto[TlIntgErrBoth]	89	1			T262	3		T263	4		T264	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9538287

1

T1

920

T2

58479

T3

736

auto[1]

21172063

1

T1

128

T2

187751

T3

80

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6036817	1			T1	751		T2	34696		T3	673
auto[TlIntgErrNone]	partial	auto[1]	16959515	1			T1	84		T2	150854		T3	44
auto[TlIntgErrNone]	full_word	auto[0]	3501327	1			T1	169		T2	23783		T3	63
auto[TlIntgErrNone]	full_word	auto[1]	4212391	1			T1	44		T2	36897		T3	36
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T263	3		T264	2		T343	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T263	3		T264	2		T343	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T344	1		T345	1		T340	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T346	1		T267	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T262	5		T263	5		T264	6
auto[TlIntgErrData]	partial	auto[1]	43	1			T262	2		T263	4		T264	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T263	1		T344	1		T345	2
auto[TlIntgErrData]	full_word	auto[1]	11	1			T264	2		T341	1		T347	3
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T262	1		T263	1		T264	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T262	1		T263	3		T264	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T264	1		T268	1		T345	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T262	1		T341	1		T348	1