Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.01	98.05	96.15	97.22		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	427725235	7144635	0	0
check_regwen_rd_A	427725235	3139	0	0
check_timeout_rd_A	427725235	2373	0	0
check_trigger_regwen_rd_A	427725235	3430	0	0
consistency_check_period_rd_A	427725235	3198	0	0
creator_sw_cfg_read_lock_rd_A	427725235	2152	0	0
direct_access_address_rd_A	427725235	1910	0	0
direct_access_wdata_0_rd_A	427725235	1209	0	0
direct_access_wdata_1_rd_A	427725235	1430	0	0
integrity_check_period_rd_A	427725235	3110	0	0
intr_enable_rd_A	427725235	4074	0	0
owner_sw_cfg_read_lock_rd_A	427725235	2262	0	0
rot_creator_auth_codesign_read_lock_rd_A	427725235	2358	0	0
rot_creator_auth_state_read_lock_rd_A	427725235	2213	0	0
vendor_test_read_lock_rd_A	427725235	2181	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	7144635	0	0
T2	219033	64589	0	0
T3	16462	0	0	0
T4	112508	0	0	0
T5	9247	0	0	0
T6	585817	130578	0	0
T7	71574	0	0	0
T8	50211	0	0	0
T9	135357	0	0	0
T10	15930	0	0	0
T11	294515	62701	0	0
T12	0	87848	0	0
T13	0	84455	0	0
T14	0	102725	0	0
T33	0	138885	0	0
T154	0	209925	0	0
T257	0	44996	0	0
T270	0	77539	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	3139	0	0
T14	604165	125	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	102	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	58	0	0
T252	0	180	0	0
T278	0	126	0	0
T326	0	36	0	0
T327	0	57	0	0
T328	0	50	0	0
T329	0	76	0	0
T330	0	22	0	0
T331	4032	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	2373	0	0
T14	604165	107	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	165	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	59	0	0
T252	0	207	0	0
T278	0	188	0	0
T326	0	60	0	0
T327	0	39	0	0
T328	0	109	0	0
T329	0	73	0	0
T330	0	54	0	0
T331	4032	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	3430	0	0
T14	604165	133	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	137	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	51	0	0
T252	0	191	0	0
T278	0	183	0	0
T326	0	97	0	0
T327	0	67	0	0
T328	0	59	0	0
T329	0	99	0	0
T330	0	23	0	0
T331	4032	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	3198	0	0
T14	604165	171	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	79	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	43	0	0
T252	0	233	0	0
T278	0	170	0	0
T326	0	108	0	0
T327	0	36	0	0
T328	0	51	0	0
T329	0	81	0	0
T330	0	25	0	0
T331	4032	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	2152	0	0
T14	604165	152	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	145	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	60	0	0
T252	0	259	0	0
T278	0	147	0	0
T326	0	64	0	0
T327	0	49	0	0
T328	0	99	0	0
T329	0	88	0	0
T330	0	37	0	0
T331	4032	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	1910	0	0
T14	604165	126	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	152	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	57	0	0
T252	0	184	0	0
T278	0	103	0	0
T326	0	95	0	0
T327	0	78	0	0
T328	0	40	0	0
T329	0	87	0	0
T330	0	65	0	0
T331	4032	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	1209	0	0
T14	604165	106	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	76	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	20	0	0
T252	0	146	0	0
T278	0	126	0	0
T326	0	53	0	0
T327	0	57	0	0
T328	0	59	0	0
T329	0	40	0	0
T330	0	21	0	0
T331	4032	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	1430	0	0
T14	604165	117	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	123	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	78	0	0
T252	0	199	0	0
T278	0	166	0	0
T326	0	74	0	0
T327	0	42	0	0
T328	0	46	0	0
T329	0	13	0	0
T330	0	22	0	0
T331	4032	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	3110	0	0
T14	604165	113	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	103	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	76	0	0
T252	0	202	0	0
T278	0	157	0	0
T326	0	47	0	0
T327	0	54	0	0
T328	0	24	0	0
T329	0	44	0	0
T330	0	31	0	0
T331	4032	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	4074	0	0
T14	604165	118	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T99	0	9	0	0
T105	18536	0	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T231	0	48	0	0
T245	0	35	0	0
T251	0	64	0	0
T252	0	231	0	0
T278	0	177	0	0
T326	0	63	0	0
T327	0	44	0	0
T328	0	42	0	0
T331	4032	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	2262	0	0
T14	604165	144	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	123	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	55	0	0
T252	0	202	0	0
T278	0	128	0	0
T326	0	84	0	0
T327	0	51	0	0
T328	0	80	0	0
T329	0	98	0	0
T330	0	24	0	0
T331	4032	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	2358	0	0
T14	604165	115	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	122	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	87	0	0
T252	0	235	0	0
T278	0	194	0	0
T326	0	81	0	0
T327	0	71	0	0
T328	0	47	0	0
T329	0	76	0	0
T330	0	33	0	0
T331	4032	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	2213	0	0
T14	604165	100	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	142	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	74	0	0
T252	0	214	0	0
T278	0	109	0	0
T326	0	82	0	0
T327	0	30	0	0
T328	0	57	0	0
T329	0	92	0	0
T330	0	49	0	0
T331	4032	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427725235	2181	0	0
T14	604165	118	0	0
T21	11653	0	0	0
T34	41639	0	0	0
T96	70582	0	0	0
T105	18536	0	0	0
T134	0	127	0	0
T154	785727	0	0	0
T155	34542	0	0	0
T177	11192	0	0	0
T229	4128	0	0	0
T251	0	73	0	0
T252	0	231	0	0
T278	0	147	0	0
T326	0	100	0	0
T327	0	36	0	0
T328	0	52	0	0
T329	0	67	0	0
T330	0	71	0	0
T331	4032	0	0	0