Module Definition
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Module : otp_ctrl_kdi
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.11 98.65 94.44 83.33 89.13 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp_ctrl_kdi 96.27 99.32 100.00 90.91 91.11 100.00



Module Instance : tb.dut.u_otp_ctrl_kdi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.27 99.32 100.00 90.91 91.11 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.21 99.63 99.64 100.00 90.91 95.70 97.37


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.01 98.05 96.15 97.22 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_flash_addr_key_anchor 100.00 100.00
u_flash_data_key_anchor 100.00 100.00
u_key_out_anchor 100.00 100.00 100.00
u_prim_count_entropy 100.00 100.00
u_prim_count_seed 100.00 100.00
u_req_arb 98.34 100.00 99.62 100.00 93.75
u_sram_data_key_anchor 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : otp_ctrl_kdi
Line No.TotalCoveredPercent
TOTAL14814698.65
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
ALWAYS25999100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN35411100.00
ALWAYS357888697.73
ALWAYS57333100.00
ALWAYS57677100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
114 1 1
115 1 1
117 1 1
118 1 1
119 1 1
148 1 1
156 1 1
164 1 1
175 4 4
176 4 4
177 4 4
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
MISSING_ELSE
265 1 1
266 1 1
MISSING_ELSE
268 1 1
269 1 1
MISSING_ELSE
284 1 1
285 1 1
286 1 1
288 1 1
289 1 1
290 1 1
293 4 4
294 4 4
295 4 4
305 1 1
354 1 1
357 1 1
360 1 1
363 1 1
364 1 1
365 1 1
366 1 1
373 1 1
376 1 1
377 1 1
378 1 1
379 1 1
382 1 1
383 1 1
384 1 1
385 1 1
387 1 1
390 1 1
392 1 1
396 1 1
397 1 1
MISSING_ELSE
403 1 1
404 1 1
405 1 1
406 1 1
MISSING_ELSE
412 1 1
413 1 1
415 1 1
416 1 1
417 1 1
MISSING_ELSE
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
430 1 1
431 1 1
434 1 1
==> MISSING_ELSE
438 1 1
439 1 1
==> MISSING_ELSE
445 1 1
446 1 1
447 1 1
448 1 1
450 1 1
451 1 1
452 1 1
455 1 1
MISSING_ELSE
462 1 1
463 1 1
464 1 1
467 1 1
468 1 1
469 1 1
470 1 1
471 1 1
==> MISSING_ELSE
474 1 1
475 1 1
MISSING_ELSE
481 1 1
482 1 1
483 1 1
484 1 1
485 1 1
MISSING_ELSE
493 1 1
494 1 1
495 1 1
497 1 1
498 1 1
501 1 1
502 0 1
505 1 1
509 1 1
511 1 1
513 1 1
514 1 1
517 0 1
MISSING_ELSE
526 1 1
527 1 1
528 1 1
530 1 1
531 1 1
532 1 1
535 1 1
MISSING_ELSE
542 1 1
543 1 1
548 1 1
562 1 1
564 1 1
565 1 1
MISSING_ELSE
573 3 3
576 1 1
577 1 1
578 1 1
579 1 1
581 1 1
582 1 1
583 1 1


Cond Coverage for Module : otp_ctrl_kdi
TotalCoveredPercent
Conditions181794.44
Logical181794.44
Non-Logical00
Event00

 LINE       305
 EXPRESSION ((data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0))
             ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       305
 SUB-EXPRESSION (data_sel == EntropyData)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       305
 SUB-EXPRESSION (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0)
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T9

 LINE       373
 EXPRESSION (edn_req_q & ((~edn_ack_i)))
             ----1----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       416
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT17,T18,T19
11CoveredT2,T3,T4

 LINE       450
 EXPRESSION (entropy_cnt == 2'b1)
            ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       497
 EXPRESSION (seed_cnt == 2'b1)
            ---------1--------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       530
 EXPRESSION (entropy_cnt == req_bundle.nonce_size)
            -------------------1------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

FSM Coverage for Module : otp_ctrl_kdi
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 24 20 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DigClrSt 404 Covered T2,T3,T4
DigEntropySt 451 Covered T2,T3,T4
DigFinSt 434 Covered T2,T3,T4
DigLoadSt 417 Covered T2,T3,T4
DigWaitSt 485 Covered T2,T3,T4
ErrorSt 564 Covered T1,T2,T4
FetchEntropySt 431 Covered T2,T3,T4
FetchNonceSt 514 Covered T2,T3,T4
FinishSt 517 Covered T2,T3,T4
IdleSt 397 Covered T1,T2,T3
ResetSt 395 Covered T1,T2,T3


transitionsLine No.CoveredTests
DigClrSt->DigLoadSt 417 Covered T2,T3,T4
DigClrSt->ErrorSt 564 Covered T12,T132,T195
DigEntropySt->DigFinSt 470 Covered T2,T3,T4
DigEntropySt->ErrorSt 564 Covered T244
DigFinSt->DigWaitSt 485 Covered T2,T3,T4
DigFinSt->ErrorSt 564 Covered T245,T130,T148
DigLoadSt->DigFinSt 434 Covered T2,T3,T4
DigLoadSt->ErrorSt 564 Covered T2,T13,T149
DigLoadSt->FetchEntropySt 431 Covered T2,T3,T4
DigWaitSt->DigClrSt 505 Covered T2,T3,T4
DigWaitSt->DigLoadSt 502 Not Covered
DigWaitSt->ErrorSt 564 Covered T246,T247,T248
DigWaitSt->FetchNonceSt 514 Covered T2,T3,T4
DigWaitSt->FinishSt 517 Not Covered
FetchEntropySt->DigEntropySt 451 Covered T2,T3,T4
FetchEntropySt->ErrorSt 564 Covered T4,T249,T250
FetchNonceSt->ErrorSt 564 Not Covered
FetchNonceSt->FinishSt 531 Covered T2,T3,T4
FinishSt->ErrorSt 564 Not Covered
FinishSt->IdleSt 542 Covered T2,T3,T4
IdleSt->DigClrSt 404 Covered T2,T3,T4
IdleSt->ErrorSt 564 Covered T1,T2,T6
ResetSt->ErrorSt 564 Covered T4,T201,T196
ResetSt->IdleSt 397 Covered T1,T2,T3



Branch Coverage for Module : otp_ctrl_kdi
Line No.TotalCoveredPercent
Branches 46 41 89.13
TERNARY 305 3 3 100.00
IF 262 2 2 100.00
IF 265 2 2 100.00
IF 268 2 2 100.00
CASE 392 31 26 83.87
IF 562 2 2 100.00
IF 573 2 2 100.00
IF 576 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 305 ((data_sel == EntropyData)) ? -2-: 305 (req_bundle.seed_valid) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T4,T7,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 262 if (key_reg_en)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 265 if (nonce_reg_en)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (seed_valid_reg_en)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 case (state_q) -2-: 396 if (kdi_en_i) -3-: 403 if (req_valid) -4-: 416 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -5-: 426 if (seed_cnt[0]) -6-: 428 if (scrmbl_ready_i) -7-: 430 if (req_bundle.ingest_entropy) -8-: 438 if (scrmbl_ready_i) -9-: 447 if (edn_ack_i) -10-: 450 if ((entropy_cnt == 2'b1)) -11-: 467 if (entropy_cnt[0]) -12-: 469 if (scrmbl_ready_i) -13-: 474 if (scrmbl_ready_i) -14-: 484 if (scrmbl_ready_i) -15-: 494 if (scrmbl_valid_i) -16-: 497 if ((seed_cnt == 2'b1)) -17-: 501 if (req_bundle.chained_digest) -18-: 513 if (req_bundle.fetch_nonce) -19-: 527 if (edn_ack_i) -20-: 530 if ((entropy_cnt == req_bundle.nonce_size))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20-StatusTests
ResetSt 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 0 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - 1 - - - - - - - - - - - - - - - - - Covered T2,T3,T4
IdleSt - 0 - - - - - - - - - - - - - - - - - Covered T1,T2,T3
DigClrSt - - 1 - - - - - - - - - - - - - - - - Covered T2,T3,T4
DigClrSt - - 0 - - - - - - - - - - - - - - - - Covered T2,T6,T11
DigLoadSt - - - 1 1 1 - - - - - - - - - - - - - Covered T2,T3,T4
DigLoadSt - - - 1 1 0 - - - - - - - - - - - - - Covered T2,T3,T4
DigLoadSt - - - 1 0 - - - - - - - - - - - - - - Not Covered
DigLoadSt - - - 0 - - 1 - - - - - - - - - - - - Covered T2,T3,T4
DigLoadSt - - - 0 - - 0 - - - - - - - - - - - - Not Covered
FetchEntropySt - - - - - - - 1 1 - - - - - - - - - - Covered T2,T3,T4
FetchEntropySt - - - - - - - 1 0 - - - - - - - - - - Covered T2,T3,T4
FetchEntropySt - - - - - - - 0 - - - - - - - - - - - Covered T2,T3,T4
DigEntropySt - - - - - - - - - 1 1 - - - - - - - - Covered T2,T3,T4
DigEntropySt - - - - - - - - - 1 0 - - - - - - - - Not Covered
DigEntropySt - - - - - - - - - 0 - 1 - - - - - - - Covered T2,T3,T4
DigEntropySt - - - - - - - - - 0 - 0 - - - - - - - Covered T2,T4,T7
DigFinSt - - - - - - - - - - - - 1 - - - - - - Covered T2,T3,T4
DigFinSt - - - - - - - - - - - - 0 - - - - - - Covered T2,T3,T4
DigWaitSt - - - - - - - - - - - - - 1 1 1 - - - Not Covered
DigWaitSt - - - - - - - - - - - - - 1 1 0 - - - Covered T2,T3,T4
DigWaitSt - - - - - - - - - - - - - 1 0 - 1 - - Covered T2,T3,T4
DigWaitSt - - - - - - - - - - - - - 1 0 - 0 - - Not Covered
DigWaitSt - - - - - - - - - - - - - 0 - - - - - Covered T2,T3,T4
FetchNonceSt - - - - - - - - - - - - - - - - - 1 1 Covered T2,T3,T4
FetchNonceSt - - - - - - - - - - - - - - - - - 1 0 Covered T2,T3,T4
FetchNonceSt - - - - - - - - - - - - - - - - - 0 - Covered T2,T3,T4
FinishSt - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
ErrorSt - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
default - - - - - - - - - - - - - - - - - - - Covered T17,T18,T19


LineNo. Expression -1-: 562 if (((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || seed_cnt_err) || entropy_cnt_err))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 573 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 576 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl_kdi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 21 21 100.00 21 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 21 21 100.00 21 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
EdnReqKnown_A 424786196 423902480 0 0
EntropyWidthDividesDigestBlockWidth_A 1146 1146 0 0
FlashOtpKeyRspKnown_A 424786196 423902480 0 0
FsmErrKnown_A 424786196 423902480 0 0
KeyNonceSize0_A 1146 1146 0 0
KeyNonceSize1_A 1146 1146 0 0
KeyNonceSize2_A 1146 1146 0 0
KeyNonceSize3_A 1146 1146 0 0
KeyNonceSize4_A 1146 1146 0 0
KeyNonceSize5_A 1146 1146 0 0
KeyNonceSize6_A 1146 1146 0 0
NonceWidth_A 1146 1146 0 0
OtbnOtpKeyRspKnown_A 424786196 423902480 0 0
ScrmblCmdKnown_A 424786196 423902480 0 0
ScrmblDataKnown_A 424786196 423902480 0 0
ScrmblModeKnown_A 424786196 423902480 0 0
ScrmblMtxReqKnown_A 424786196 423902480 0 0
ScrmblSelKnown_A 424786196 423902480 0 0
ScrmblValidKnown_A 424786196 423902480 0 0
SramOtpKeyRspKnown_A 424786196 423902480 0 0
u_state_regs_A 424786196 423902480 0 0


EdnReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

EntropyWidthDividesDigestBlockWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

FlashOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

FsmErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

KeyNonceSize0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize4_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize5_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize6_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NonceWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OtbnOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblModeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblMtxReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

SramOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_kdi
Line No.TotalCoveredPercent
TOTAL14714699.32
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
ALWAYS25999100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN35411100.00
ALWAYS357878698.85
ALWAYS57333100.00
ALWAYS57677100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
114 1 1
115 1 1
117 1 1
118 1 1
119 1 1
148 1 1
156 1 1
164 1 1
175 4 4
176 4 4
177 4 4
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
MISSING_ELSE
265 1 1
266 1 1
MISSING_ELSE
268 1 1
269 1 1
MISSING_ELSE
284 1 1
285 1 1
286 1 1
288 1 1
289 1 1
290 1 1
293 4 4
294 4 4
295 4 4
305 1 1
354 1 1
357 1 1
360 1 1
363 1 1
364 1 1
365 1 1
366 1 1
373 1 1
376 1 1
377 1 1
378 1 1
379 1 1
382 1 1
383 1 1
384 1 1
385 1 1
387 1 1
390 1 1
392 1 1
396 1 1
397 1 1
MISSING_ELSE
403 1 1
404 1 1
405 1 1
406 1 1
MISSING_ELSE
412 1 1
413 1 1
415 1 1
416 1 1
417 1 1
MISSING_ELSE
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
430 1 1
431 1 1
434 1 1
==> MISSING_ELSE
438 1 1
439 1 1
==> MISSING_ELSE
445 1 1
446 1 1
447 1 1
448 1 1
450 1 1
451 1 1
452 1 1
455 1 1
MISSING_ELSE
462 1 1
463 1 1
464 1 1
467 1 1
468 1 1
469 1 1
470 1 1
471 1 1
==> MISSING_ELSE
474 1 1
475 1 1
MISSING_ELSE
481 1 1
482 1 1
483 1 1
484 1 1
485 1 1
MISSING_ELSE
493 1 1
494 1 1
495 1 1
497 1 1
498 1 1
501 1 1
502 excluded
Exclude Annotation: VC_COV_UNR
505 1 1
509 1 1
511 1 1
513 1 1
514 1 1
517 0 1
MISSING_ELSE
526 1 1
527 1 1
528 1 1
530 1 1
531 1 1
532 1 1
535 1 1
MISSING_ELSE
542 1 1
543 1 1
548 1 1
562 1 1
564 1 1
565 1 1
MISSING_ELSE
573 3 3
576 1 1
577 1 1
578 1 1
579 1 1
581 1 1
582 1 1
583 1 1


Cond Coverage for Instance : tb.dut.u_otp_ctrl_kdi
TotalCoveredPercent
Conditions1717100.00
Logical1717100.00
Non-Logical00
Event00

 LINE       305
 EXPRESSION ((data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0))
             ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       305
 SUB-EXPRESSION (data_sel == EntropyData)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       305
 SUB-EXPRESSION (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0)
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T9

 LINE       373
 EXPRESSION (edn_req_q & ((~edn_ack_i)))
             ----1----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       416
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT17,T18,T19
11CoveredT2,T3,T4

 LINE       450
 EXPRESSION (entropy_cnt == 2'b1)
            ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       497
 EXPRESSION (seed_cnt == 2'b1)
            ---------1--------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       530
 EXPRESSION (entropy_cnt == req_bundle.nonce_size)
            -------------------1------------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

FSM Coverage for Instance : tb.dut.u_otp_ctrl_kdi
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 22 20 90.91
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DigClrSt 404 Covered T2,T3,T4
DigEntropySt 451 Covered T2,T3,T4
DigFinSt 434 Covered T2,T3,T4
DigLoadSt 417 Covered T2,T3,T4
DigWaitSt 485 Covered T2,T3,T4
ErrorSt 564 Covered T1,T2,T4
FetchEntropySt 431 Covered T2,T3,T4
FetchNonceSt 514 Covered T2,T3,T4
FinishSt 517 Covered T2,T3,T4
IdleSt 397 Covered T1,T2,T3
ResetSt 395 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
DigClrSt->DigLoadSt 417 Covered T2,T3,T4
DigClrSt->ErrorSt 564 Covered T12,T132,T195
DigEntropySt->DigFinSt 470 Covered T2,T3,T4
DigEntropySt->ErrorSt 564 Covered T244
DigFinSt->DigWaitSt 485 Covered T2,T3,T4
DigFinSt->ErrorSt 564 Covered T245,T130,T148
DigLoadSt->DigFinSt 434 Covered T2,T3,T4
DigLoadSt->ErrorSt 564 Covered T2,T13,T149
DigLoadSt->FetchEntropySt 431 Covered T2,T3,T4
DigWaitSt->DigClrSt 505 Covered T2,T3,T4
DigWaitSt->DigLoadSt 502 Excluded VC_COV_UNR
DigWaitSt->ErrorSt 564 Covered T246,T247,T248
DigWaitSt->FetchNonceSt 514 Covered T2,T3,T4
DigWaitSt->FinishSt 517 Excluded
FetchEntropySt->DigEntropySt 451 Covered T2,T3,T4
FetchEntropySt->ErrorSt 564 Covered T4,T249,T250
FetchNonceSt->ErrorSt 564 Not Covered
FetchNonceSt->FinishSt 531 Covered T2,T3,T4
FinishSt->ErrorSt 564 Not Covered
FinishSt->IdleSt 542 Covered T2,T3,T4
IdleSt->DigClrSt 404 Covered T2,T3,T4
IdleSt->ErrorSt 564 Covered T1,T2,T6
ResetSt->ErrorSt 564 Covered T4,T201,T196
ResetSt->IdleSt 397 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_otp_ctrl_kdi
Line No.TotalCoveredPercent
Branches 45 41 91.11
TERNARY 305 3 3 100.00
IF 262 2 2 100.00
IF 265 2 2 100.00
IF 268 2 2 100.00
CASE 392 30 26 86.67
IF 562 2 2 100.00
IF 573 2 2 100.00
IF 576 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 305 ((data_sel == EntropyData)) ? -2-: 305 (req_bundle.seed_valid) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T4,T7,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 262 if (key_reg_en)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 265 if (nonce_reg_en)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (seed_valid_reg_en)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 case (state_q) -2-: 396 if (kdi_en_i) -3-: 403 if (req_valid) -4-: 416 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -5-: 426 if (seed_cnt[0]) -6-: 428 if (scrmbl_ready_i) -7-: 430 if (req_bundle.ingest_entropy) -8-: 438 if (scrmbl_ready_i) -9-: 447 if (edn_ack_i) -10-: 450 if ((entropy_cnt == 2'b1)) -11-: 467 if (entropy_cnt[0]) -12-: 469 if (scrmbl_ready_i) -13-: 474 if (scrmbl_ready_i) -14-: 484 if (scrmbl_ready_i) -15-: 494 if (scrmbl_valid_i) -16-: 497 if ((seed_cnt == 2'b1)) -17-: 501 if (req_bundle.chained_digest) -18-: 513 if (req_bundle.fetch_nonce) -19-: 527 if (edn_ack_i) -20-: 530 if ((entropy_cnt == req_bundle.nonce_size))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20-StatusTestsExclude Annotation
ResetSt 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 0 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - 1 - - - - - - - - - - - - - - - - - Covered T2,T3,T4
IdleSt - 0 - - - - - - - - - - - - - - - - - Covered T1,T2,T3
DigClrSt - - 1 - - - - - - - - - - - - - - - - Covered T2,T3,T4
DigClrSt - - 0 - - - - - - - - - - - - - - - - Covered T2,T6,T11
DigLoadSt - - - 1 1 1 - - - - - - - - - - - - - Covered T2,T3,T4
DigLoadSt - - - 1 1 0 - - - - - - - - - - - - - Covered T2,T3,T4
DigLoadSt - - - 1 0 - - - - - - - - - - - - - - Not Covered
DigLoadSt - - - 0 - - 1 - - - - - - - - - - - - Covered T2,T3,T4
DigLoadSt - - - 0 - - 0 - - - - - - - - - - - - Not Covered
FetchEntropySt - - - - - - - 1 1 - - - - - - - - - - Covered T2,T3,T4
FetchEntropySt - - - - - - - 1 0 - - - - - - - - - - Covered T2,T3,T4
FetchEntropySt - - - - - - - 0 - - - - - - - - - - - Covered T2,T3,T4
DigEntropySt - - - - - - - - - 1 1 - - - - - - - - Covered T2,T3,T4
DigEntropySt - - - - - - - - - 1 0 - - - - - - - - Not Covered
DigEntropySt - - - - - - - - - 0 - 1 - - - - - - - Covered T2,T3,T4
DigEntropySt - - - - - - - - - 0 - 0 - - - - - - - Covered T2,T4,T7
DigFinSt - - - - - - - - - - - - 1 - - - - - - Covered T2,T3,T4
DigFinSt - - - - - - - - - - - - 0 - - - - - - Covered T2,T3,T4
DigWaitSt - - - - - - - - - - - - - 1 1 1 - - - Excluded VC_COV_UNR
DigWaitSt - - - - - - - - - - - - - 1 1 0 - - - Covered T2,T3,T4
DigWaitSt - - - - - - - - - - - - - 1 0 - 1 - - Covered T2,T3,T4
DigWaitSt - - - - - - - - - - - - - 1 0 - 0 - - Not Covered
DigWaitSt - - - - - - - - - - - - - 0 - - - - - Covered T2,T3,T4
FetchNonceSt - - - - - - - - - - - - - - - - - 1 1 Covered T2,T3,T4
FetchNonceSt - - - - - - - - - - - - - - - - - 1 0 Covered T2,T3,T4
FetchNonceSt - - - - - - - - - - - - - - - - - 0 - Covered T2,T3,T4
FinishSt - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
ErrorSt - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
default - - - - - - - - - - - - - - - - - - - Covered T17,T18,T19


LineNo. Expression -1-: 562 if (((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || seed_cnt_err) || entropy_cnt_err))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 573 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 576 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_ctrl_kdi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 21 21 100.00 21 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 21 21 100.00 21 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
EdnReqKnown_A 424786196 423902480 0 0
EntropyWidthDividesDigestBlockWidth_A 1146 1146 0 0
FlashOtpKeyRspKnown_A 424786196 423902480 0 0
FsmErrKnown_A 424786196 423902480 0 0
KeyNonceSize0_A 1146 1146 0 0
KeyNonceSize1_A 1146 1146 0 0
KeyNonceSize2_A 1146 1146 0 0
KeyNonceSize3_A 1146 1146 0 0
KeyNonceSize4_A 1146 1146 0 0
KeyNonceSize5_A 1146 1146 0 0
KeyNonceSize6_A 1146 1146 0 0
NonceWidth_A 1146 1146 0 0
OtbnOtpKeyRspKnown_A 424786196 423902480 0 0
ScrmblCmdKnown_A 424786196 423902480 0 0
ScrmblDataKnown_A 424786196 423902480 0 0
ScrmblModeKnown_A 424786196 423902480 0 0
ScrmblMtxReqKnown_A 424786196 423902480 0 0
ScrmblSelKnown_A 424786196 423902480 0 0
ScrmblValidKnown_A 424786196 423902480 0 0
SramOtpKeyRspKnown_A 424786196 423902480 0 0
u_state_regs_A 424786196 423902480 0 0


EdnReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

EntropyWidthDividesDigestBlockWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

FlashOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

FsmErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

KeyNonceSize0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize4_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize5_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

KeyNonceSize6_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NonceWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OtbnOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblModeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblMtxReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

ScrmblValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

SramOtpKeyRspKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%