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Module Instance : tb.dut.u_scrmbl_mtx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.48 75.00 99.17 100.00 43.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.48 75.00 99.17 100.00 43.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.01 98.05 96.15 97.22 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.u_scrmbl_mtx
Line Coverage for Instance : tb.dut.u_scrmbl_mtx
Line No.TotalCoveredPercent
TOTAL19214475.00
CONT_ASSIGN6200
CONT_ASSIGN112100.00
CONT_ASSIGN112100.00
CONT_ASSIGN112100.00
CONT_ASSIGN112100.00
CONT_ASSIGN112100.00
CONT_ASSIGN11211100.00
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CONT_ASSIGN11211100.00
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CONT_ASSIGN112100.00
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CONT_ASSIGN112100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
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CONT_ASSIGN11811100.00
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CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
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CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN148100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN148100.00
CONT_ASSIGN148100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14800
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
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CONT_ASSIGN150100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15000
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN151100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN151100.00
CONT_ASSIGN151100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15100
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN155100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN155100.00
CONT_ASSIGN155100.00
CONT_ASSIGN155100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN155100.00
CONT_ASSIGN155100.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN156100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN156100.00
CONT_ASSIGN156100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN156100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN160100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN160100.00
CONT_ASSIGN160100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
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CONT_ASSIGN16011100.00
CONT_ASSIGN16000
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN161100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN161100.00
CONT_ASSIGN161100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16300
CONT_ASSIGN163100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16300
CONT_ASSIGN163100.00
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CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
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CONT_ASSIGN16411100.00
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CONT_ASSIGN16411100.00
CONT_ASSIGN164100.00
CONT_ASSIGN16411100.00
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CONT_ASSIGN164100.00
CONT_ASSIGN164100.00
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CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 7 14
118 14 14
122 7 14
126 unreachable
128 14 14
138 2 2
148 11 14(1 unreachable)
150 11 14(1 unreachable)
151 11 14(1 unreachable)
155 8 15
156 11 15
160 11 14(1 unreachable)
161 12 15
163 8 11(4 unreachable)
164 10 15
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_scrmbl_mtx
TotalCoveredPercent
Conditions36235999.17
Logical36235999.17
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
118-16098.93
160-164100.00

Branch Coverage for Instance : tb.dut.u_scrmbl_mtx
Line No.TotalCoveredPercent
Branches 74 74 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 155 1 1 100.00
TERNARY 156 1 1 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_scrmbl_mtx
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 7 43.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 7 43.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 424786196 423902480 0 0
CheckNGreaterZero_A 1146 1146 0 0
GntImpliesReady_A 424786196 0 0 0
GntImpliesValid_A 424786196 0 0 0
GrantKnown_A 424786196 423902480 0 0
IdxKnown_A 424786196 423902480 0 0
IndexIsCorrect_A 424786196 0 0 0
LockArbDecision_A 424786196 0 0 0
NoReadyValidNoGrant_A 424786196 381160122 0 0
ReadyAndValidImplyGrant_A 424786196 0 0 0
ReqAndReadyImplyGrant_A 424786196 0 0 0
ReqImpliesValid_A 424786196 42742358 0 0
ReqStaysHighUntilGranted0_M 424786196 0 0 0
RoundRobin_A 424786196 0 0 1146
ValidKnown_A 424786196 423902480 0 0
gen_data_port_assertion.DataFlow_A 424786196 0 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146 1146 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 381160122 0 0
T1 9526 3535 0 0
T2 219033 212570 0 0
T3 16462 5583 0 0
T4 112508 623650 0 0
T5 9247 6069 0 0
T6 585817 571118 0 0
T7 71574 40022 0 0
T8 50211 18868 0 0
T9 135357 78980 0 0
T10 15930 10632 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 42742358 0 0
T1 9526 5715 0 0
T2 219033 64496 0 0
T3 16462 10558 0 0
T4 112508 488822 0 0
T5 9247 2909 0 0
T6 585817 146875 0 0
T7 71574 30687 0 0
T8 50211 31079 0 0
T9 135357 54895 0 0
T10 15930 4993 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 1146

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 423902480 0 0
T1 9526 9250 0 0
T2 219033 219019 0 0
T3 16462 16141 0 0
T4 112508 111247 0 0
T5 9247 8978 0 0
T6 585817 585805 0 0
T7 71574 70709 0 0
T8 50211 49947 0 0
T9 135357 133875 0 0
T10 15930 15625 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424786196 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%