Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23935164

1

T1

1285

T2

6128

T3

279417

full_word

7936530

1

T1

203

T2

2700

T3

80346

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31871404	1			T1	1488		T2	8828		T3	359763
auto[TlIntgErrCmd]	85	1			T244	6		T245	6		T254	5
auto[TlIntgErrData]	110	1			T244	8		T245	8		T246	7
auto[TlIntgErrBoth]	95	1			T244	6		T245	6		T246	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9340616

1

T1

1438

T2

8103

T3

63359

auto[1]

22531078

1

T1

50

T2

725

T3

296404

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5873455	1			T1	1256		T2	5686		T3	40717
auto[TlIntgErrNone]	partial	auto[1]	18061449	1			T1	29		T2	442		T3	238700
auto[TlIntgErrNone]	full_word	auto[0]	3467019	1			T1	182		T2	2417		T3	22642
auto[TlIntgErrNone]	full_word	auto[1]	4469481	1			T1	21		T2	283		T3	57704
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T244	2		T254	1		T255	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T244	4		T245	5		T254	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T245	1		T254	1		T252	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T328	1		T333	1		T329	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T244	1		T245	5		T246	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T244	5		T245	3		T246	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T244	1		T246	1		T329	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T244	1		T328	1		T334	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T244	4		T245	2		T246	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T244	2		T245	4		T246	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T333	1		T332	1		T335	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T329	1		T335	1		T253	2