Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	460975023	7656903	0	0
check_regwen_rd_A	460975023	3547	0	0
check_timeout_rd_A	460975023	3291	0	0
check_trigger_regwen_rd_A	460975023	3574	0	0
consistency_check_period_rd_A	460975023	3830	0	0
creator_sw_cfg_read_lock_rd_A	460975023	2907	0	0
direct_access_address_rd_A	460975023	2674	0	0
direct_access_wdata_0_rd_A	460975023	1553	0	0
direct_access_wdata_1_rd_A	460975023	1883	0	0
integrity_check_period_rd_A	460975023	3701	0	0
intr_enable_rd_A	460975023	4359	0	0
owner_sw_cfg_read_lock_rd_A	460975023	2804	0	0
rot_creator_auth_codesign_read_lock_rd_A	460975023	2980	0	0
rot_creator_auth_state_read_lock_rd_A	460975023	2828	0	0
vendor_test_read_lock_rd_A	460975023	2590	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	7656903	0	0
T3	588527	105603	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T13	0	147538	0	0
T14	0	45646	0	0
T15	0	21400	0	0
T16	0	164295	0	0
T35	0	68145	0	0
T105	0	162983	0	0
T119	0	52903	0	0
T256	0	33189	0	0
T257	0	40757	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	3547	0	0
T3	588527	73	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	78	0	0
T15	0	41	0	0
T16	0	113	0	0
T105	0	192	0	0
T235	0	72	0	0
T257	0	101	0	0
T263	0	125	0	0
T319	0	63	0	0
T320	0	86	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	3291	0	0
T3	588527	72	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	71	0	0
T15	0	31	0	0
T16	0	114	0	0
T105	0	198	0	0
T235	0	41	0	0
T257	0	56	0	0
T263	0	142	0	0
T319	0	44	0	0
T320	0	92	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	3574	0	0
T3	588527	69	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	48	0	0
T15	0	38	0	0
T16	0	95	0	0
T105	0	204	0	0
T235	0	60	0	0
T257	0	51	0	0
T263	0	110	0	0
T319	0	57	0	0
T320	0	96	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	3830	0	0
T3	588527	60	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	71	0	0
T15	0	53	0	0
T16	0	106	0	0
T105	0	177	0	0
T235	0	64	0	0
T257	0	45	0	0
T263	0	139	0	0
T319	0	46	0	0
T320	0	115	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	2907	0	0
T3	588527	92	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	64	0	0
T15	0	63	0	0
T16	0	104	0	0
T105	0	212	0	0
T235	0	85	0	0
T257	0	56	0	0
T263	0	143	0	0
T319	0	48	0	0
T320	0	81	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	2674	0	0
T3	588527	57	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	111	0	0
T15	0	30	0	0
T16	0	129	0	0
T105	0	227	0	0
T235	0	38	0	0
T257	0	49	0	0
T263	0	169	0	0
T319	0	86	0	0
T320	0	89	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	1553	0	0
T3	588527	63	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	49	0	0
T15	0	12	0	0
T16	0	134	0	0
T105	0	99	0	0
T235	0	17	0	0
T257	0	29	0	0
T263	0	72	0	0
T319	0	23	0	0
T320	0	66	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	1883	0	0
T3	588527	25	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	37	0	0
T15	0	6	0	0
T16	0	77	0	0
T105	0	139	0	0
T235	0	22	0	0
T257	0	43	0	0
T263	0	136	0	0
T319	0	48	0	0
T320	0	90	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	3701	0	0
T3	588527	60	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	75	0	0
T15	0	38	0	0
T16	0	114	0	0
T105	0	170	0	0
T235	0	54	0	0
T257	0	57	0	0
T263	0	126	0	0
T319	0	58	0	0
T320	0	109	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	4359	0	0
T3	588527	74	0	0
T4	148043	9	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	103	0	0
T15	0	40	0	0
T16	0	127	0	0
T67	0	3	0	0
T99	0	37	0	0
T105	0	255	0	0
T235	0	58	0	0
T257	0	58	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	2804	0	0
T3	588527	67	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	51	0	0
T15	0	78	0	0
T16	0	109	0	0
T105	0	182	0	0
T235	0	85	0	0
T257	0	45	0	0
T263	0	129	0	0
T319	0	59	0	0
T320	0	64	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	2980	0	0
T3	588527	78	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	41	0	0
T15	0	35	0	0
T16	0	70	0	0
T105	0	238	0	0
T235	0	56	0	0
T257	0	42	0	0
T263	0	102	0	0
T319	0	57	0	0
T320	0	75	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	2828	0	0
T3	588527	44	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	59	0	0
T15	0	17	0	0
T16	0	96	0	0
T105	0	136	0	0
T235	0	41	0	0
T257	0	90	0	0
T263	0	162	0	0
T319	0	63	0	0
T320	0	94	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460975023	2590	0	0
T3	588527	31	0	0
T4	148043	0	0	0
T5	86149	0	0	0
T6	14442	0	0	0
T7	60989	0	0	0
T8	5660	0	0	0
T9	95512	0	0	0
T10	68812	0	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T14	0	37	0	0
T15	0	34	0	0
T16	0	83	0	0
T105	0	239	0	0
T235	0	68	0	0
T257	0	40	0	0
T263	0	105	0	0
T319	0	41	0	0
T320	0	74	0	0