Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T7,T9
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T161
1	Covered	T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T3,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T7,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T7
ReadWaitSt	252	Covered	T2,T7,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T7
IdleSt->ReadSt	236	Covered	T2,T3,T7
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T203,T204,T205
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T7
ReadSt->ReadWaitSt	252	Covered	T2,T7,T9
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T7,T9
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T3,T7
CheckFailError	317	Covered	T161
FsmStateError	289	Covered	T2,T3,T7
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T7,T4,T14
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T3,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T161
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T7
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T3,T7
NoError->CheckFailError	317	Covered	T161
NoError->FsmStateError	289	Covered	T2,T3,T11
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T7,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T10,T4,T67
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T7,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T7,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T161
1	0	Covered	T161
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	457920798	457065238	0	0
DigestKnown_A	457920798	457065238	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	457920798	2790	0	0
ErrorKnown_A	457920798	457065238	0	0
FsmStateKnown_A	457920798	457065238	0	0
InitDoneKnown_A	457920798	457065238	0	0
InitReadLocksPartition_A	457920798	91915798	0	0
InitWriteLocksPartition_A	457920798	91915798	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	457920798	457065238	0	0
OtpCmdKnown_A	457920798	457065238	0	0
OtpErrorState_A	457920798	0	0	0
OtpReqKnown_A	457920798	457065238	0	0
OtpSizeKnown_A	457920798	457065238	0	0
OtpWdataKnown_A	457920798	457065238	0	0
ReadLockPropagation_A	457920798	189663047	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	457920798	457065238	0	0
TlulRdataKnown_A	457920798	457065238	0	0
TlulReadOnReadLock_A	457920798	7593	0	0
TlulRerrorKnown_A	457920798	457065238	0	0
TlulRvalidKnown_A	457920798	457065238	0	0
WriteLockPropagation_A	457920798	2065939	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	457920798	26202879	0	0
u_state_regs_A	457920798	457065238	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	2790	0	0
T58	71645	0	0	0
T161	11665	2790	0	0
T172	15312	0	0	0
T173	127610	0	0	0
T174	4062	0	0	0
T175	14402	0	0	0
T176	26869	0	0	0
T177	686499	0	0	0
T178	19245	0	0	0
T179	16790	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	91915798	0	0
T1	13402	916	0	0
T2	71262	7973	0	0
T3	588527	960063	0	0
T6	14442	166	0	0
T7	60989	45754	0	0
T8	5660	219	0	0
T9	95512	563	0	0
T10	68812	1020	0	0
T11	13511	4060	0	0
T12	15491	5117	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	91915798	0	0
T1	13402	916	0	0
T2	71262	7973	0	0
T3	588527	960063	0	0
T6	14442	166	0	0
T7	60989	45754	0	0
T8	5660	219	0	0
T9	95512	563	0	0
T10	68812	1020	0	0
T11	13511	4060	0	0
T12	15491	5117	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	189663047	0	0
T2	71262	3473	0	0
T3	588527	748328	0	0
T4	148043	156982	0	0
T6	14442	0	0	0
T7	60989	47251	0	0
T8	5660	0	0	0
T9	95512	26271	0	0
T10	68812	6669	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T13	0	650521	0	0
T36	0	223	0	0
T37	0	4167	0	0
T70	0	2850	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	7593	0	0
T2	71262	11	0	0
T3	588527	20	0	0
T4	148043	35	0	0
T5	0	13	0	0
T6	14442	0	0	0
T7	60989	12	0	0
T8	5660	0	0	0
T9	95512	3	0	0
T10	68812	14	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T13	0	9	0	0
T70	0	1	0	0
T165	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	2065939	0	0
T4	148043	116393	0	0
T5	86149	0	0	0
T10	68812	8121	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T36	60811	2415	0	0
T37	0	3237	0	0
T48	15186	0	0	0
T50	13852	0	0	0
T66	0	13011	0	0
T67	0	89683	0	0
T89	14013	0	0	0
T96	32789	0	0	0
T97	0	891	0	0
T98	0	3063	0	0
T99	0	40245	0	0
T100	0	23048	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	26202879	0	0
T4	148043	660179	0	0
T5	86149	0	0	0
T7	60989	2586	0	0
T8	5660	0	0	0
T9	95512	75240	0	0
T10	68812	59595	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T36	0	36769	0	0
T37	0	33887	0	0
T48	15186	0	0	0
T70	0	9144	0	0
T89	14013	7514	0	0
T139	0	4326	0	0
T152	0	42677	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T89,T69

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T9,T152

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T144,T158,T162
1	Covered	T144,T158,T162

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T3,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T7
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T203,T204,T205
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T68,T106,T107
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T6
ReadWaitSt->ErrorSt	276	Covered	T152,T154,T188
ReadWaitSt->IdleSt	270	Covered	T1,T2,T6
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T7
CheckFailError	317	Covered	T144,T158,T162
FsmStateError	289	Covered	T2,T3,T7
MacroEccCorrError	221	Covered	T2,T9,T11
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T4,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T144,T158,T162
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T11,T89,T152
MacroEccCorrError->NoError	235	Covered	T2,T9,T66
NoError->AccessError	256	Covered	T2,T3,T7
NoError->CheckFailError	317	Covered	T144,T158,T162
NoError->FsmStateError	289	Covered	T2,T3,T12
NoError->MacroEccCorrError	221	Covered	T2,T9,T11

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T11,T89,T69
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T68,T106,T107
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T10,T4,T67
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T9,T152
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T152,T154,T188
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T144,T158,T162
1	0	Covered	T144,T158,T162
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	457920798	457065238	0	0
DigestKnown_A	457920798	457065238	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	457920798	7113	0	0
ErrorKnown_A	457920798	457065238	0	0
FsmStateKnown_A	457920798	457065238	0	0
InitDoneKnown_A	457920798	457065238	0	0
InitReadLocksPartition_A	457920798	92095174	0	0
InitWriteLocksPartition_A	457920798	92095174	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	457920798	457065238	0	0
OtpCmdKnown_A	457920798	457065238	0	0
OtpErrorState_A	457920798	73	0	0
OtpReqKnown_A	457920798	457065238	0	0
OtpSizeKnown_A	457920798	457065238	0	0
OtpWdataKnown_A	457920798	457065238	0	0
ReadLockPropagation_A	457920798	189918463	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	457920798	457065238	0	0
TlulRdataKnown_A	457920798	457065238	0	0
TlulReadOnReadLock_A	457920798	8021	0	0
TlulRerrorKnown_A	457920798	457065238	0	0
TlulRvalidKnown_A	457920798	457065238	0	0
WriteLockPropagation_A	457920798	1778462	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	457920798	25975067	0	0
u_state_regs_A	457920798	457065238	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	7113	0	0
T24	12421	0	0	0
T59	13814	0	0	0
T108	16130	0	0	0
T144	8657	2433	0	0
T158	0	2127	0	0
T162	0	2553	0	0
T166	45541	0	0	0
T167	13893	0	0	0
T168	10995	0	0	0
T169	148519	0	0	0
T170	11921	0	0	0
T171	52596	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	92095174	0	0
T1	13402	967	0	0
T2	71262	8279	0	0
T3	588527	960199	0	0
T6	14442	217	0	0
T7	60989	45788	0	0
T8	5660	236	0	0
T9	95512	750	0	0
T10	68812	1360	0	0
T11	13511	4111	0	0
T12	15491	5151	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	92095174	0	0
T1	13402	967	0	0
T2	71262	8279	0	0
T3	588527	960199	0	0
T6	14442	217	0	0
T7	60989	45788	0	0
T8	5660	236	0	0
T9	95512	750	0	0
T10	68812	1360	0	0
T11	13511	4111	0	0
T12	15491	5151	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	73	0	0
T14	249099	0	0	0
T68	12166	1	0	0
T106	15114	1	0	0
T107	11480	1	0	0
T139	82470	0	0	0
T152	187579	1	0	0
T154	0	1	0	0
T165	18656	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T194	4314	0	0	0
T195	33523	0	0	0
T196	14829	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	189918463	0	0
T2	71262	3250	0	0
T3	588527	769639	0	0
T4	148043	246186	0	0
T6	14442	0	0	0
T7	60989	53184	0	0
T8	5660	0	0	0
T9	95512	37513	0	0
T10	68812	6850	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T13	0	579655	0	0
T36	0	444	0	0
T37	0	1729	0	0
T70	0	2838	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	8021	0	0
T2	71262	11	0	0
T3	588527	22	0	0
T4	148043	20	0	0
T5	0	15	0	0
T6	14442	0	0	0
T7	60989	17	0	0
T8	5660	0	0	0
T9	95512	2	0	0
T10	68812	11	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T13	0	16	0	0
T70	0	3	0	0
T165	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	1778462	0	0
T4	148043	11294	0	0
T5	86149	0	0	0
T10	68812	5074	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T36	60811	0	0	0
T37	0	1777	0	0
T48	15186	0	0	0
T50	13852	0	0	0
T67	0	118070	0	0
T86	0	10880	0	0
T89	14013	0	0	0
T96	32789	0	0	0
T97	0	891	0	0
T99	0	27637	0	0
T100	0	11338	0	0
T101	0	1983	0	0
T118	0	37405	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	25975067	0	0
T4	148043	636080	0	0
T5	86149	0	0	0
T7	60989	2569	0	0
T8	5660	0	0	0
T9	95512	75087	0	0
T10	68812	59289	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T37	0	18838	0	0
T48	15186	0	0	0
T68	0	2219	0	0
T70	0	9110	0	0
T89	14013	0	0	0
T106	0	3816	0	0
T139	0	4292	0	0
T195	0	2685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T89,T155,T156

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T9,T152

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T144,T157,T158
1	Covered	T144,T157,T158

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T3,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T4,T36

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T4,T36

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T6
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T7
IdleSt->ReadSt	236	Covered	T2,T3,T6
InitSt->ErrorSt	315	Covered	T203,T204,T205
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T68,T106,T107
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T7
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T148,T164,T184
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T7
CheckFailError	317	Covered	T144,T157,T158
FsmStateError	289	Covered	T2,T3,T7
MacroEccCorrError	221	Covered	T2,T9,T89
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T4,T165
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T144,T157,T158
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T89,T152,T155
MacroEccCorrError->NoError	235	Covered	T2,T9,T66
NoError->AccessError	256	Covered	T2,T3,T7
NoError->CheckFailError	317	Covered	T144,T157,T158
NoError->FsmStateError	289	Covered	T2,T3,T11
NoError->MacroEccCorrError	221	Covered	T2,T9,T89

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T4,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T89,T155,T156
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T183,T189,T190
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T10,T67,T99
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T9,T152
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T148,T164,T184
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T144,T157,T158
1	0	Covered	T144,T157,T158
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	457920798	457065238	0	0
DigestKnown_A	457920798	457065238	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	457920798	11682	0	0
ErrorKnown_A	457920798	457065238	0	0
FsmStateKnown_A	457920798	457065238	0	0
InitDoneKnown_A	457920798	457065238	0	0
InitReadLocksPartition_A	457920798	92273462	0	0
InitWriteLocksPartition_A	457920798	92273462	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	457920798	457065238	0	0
OtpCmdKnown_A	457920798	457065238	0	0
OtpErrorState_A	457920798	53	0	0
OtpReqKnown_A	457920798	457065238	0	0
OtpSizeKnown_A	457920798	457065238	0	0
OtpWdataKnown_A	457920798	457065238	0	0
ReadLockPropagation_A	457920798	190410217	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	457920798	457065238	0	0
TlulRdataKnown_A	457920798	457065238	0	0
TlulReadOnReadLock_A	457920798	8077	0	0
TlulRerrorKnown_A	457920798	457065238	0	0
TlulRvalidKnown_A	457920798	457065238	0	0
WriteLockPropagation_A	457920798	1277794	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	457920798	16578359	0	0
u_state_regs_A	457920798	457065238	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	11682	0	0
T24	12421	0	0	0
T59	13814	0	0	0
T108	16130	0	0	0
T144	8657	2433	0	0
T157	0	3703	0	0
T158	0	2127	0	0
T160	0	3419	0	0
T166	45541	0	0	0
T167	13893	0	0	0
T168	10995	0	0	0
T169	148519	0	0	0
T170	11921	0	0	0
T171	52596	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	92273462	0	0
T1	13402	1018	0	0
T2	71262	8585	0	0
T3	588527	960335	0	0
T6	14442	268	0	0
T7	60989	45822	0	0
T8	5660	253	0	0
T9	95512	937	0	0
T10	68812	1700	0	0
T11	13511	4162	0	0
T12	15491	5185	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	92273462	0	0
T1	13402	1018	0	0
T2	71262	8585	0	0
T3	588527	960335	0	0
T6	14442	268	0	0
T7	60989	45822	0	0
T8	5660	253	0	0
T9	95512	937	0	0
T10	68812	1700	0	0
T11	13511	4162	0	0
T12	15491	5185	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	53	0	0
T78	32504	0	0	0
T97	57526	0	0	0
T101	42724	0	0	0
T148	127401	1	0	0
T164	0	1	0	0
T180	8557	0	0	0
T181	12254	0	0	0
T182	15395	0	0	0
T183	0	1	0	0
T184	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T197	31013	0	0	0
T198	54661	0	0	0
T199	7733	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	190410217	0	0
T2	71262	2157	0	0
T3	588527	769624	0	0
T4	148043	209477	0	0
T6	14442	0	0	0
T7	60989	50661	0	0
T8	5660	0	0	0
T9	95512	39259	0	0
T10	68812	7421	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T13	0	570253	0	0
T36	0	223	0	0
T70	0	4881	0	0
T165	0	10182	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	8077	0	0
T2	71262	3	0	0
T3	588527	18	0	0
T4	148043	19	0	0
T5	0	11	0	0
T6	14442	0	0	0
T7	60989	16	0	0
T8	5660	0	0	0
T9	95512	4	0	0
T10	68812	11	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T13	0	9	0	0
T14	0	40	0	0
T165	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	1277794	0	0
T4	148043	14711	0	0
T5	86149	0	0	0
T10	68812	5393	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T36	60811	305	0	0
T48	15186	0	0	0
T50	13852	0	0	0
T66	0	10335	0	0
T67	0	142764	0	0
T89	14013	0	0	0
T96	32789	0	0	0
T97	0	1074	0	0
T99	0	20626	0	0
T101	0	1983	0	0
T102	0	8142	0	0
T118	0	32125	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	16578359	0	0
T4	148043	122692	0	0
T5	86149	0	0	0
T10	68812	58983	0	0
T11	13511	0	0	0
T12	15491	0	0	0
T36	60811	36497	0	0
T37	0	33615	0	0
T48	15186	0	0	0
T50	13852	0	0	0
T66	0	150004	0	0
T67	0	863586	0	0
T70	0	20705	0	0
T89	14013	0	0	0
T96	32789	0	0	0
T148	0	21443	0	0
T195	0	2668	0	0
T196	0	4157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457920798	457065238	0	0
T1	13402	13155	0	0
T2	71262	69856	0	0
T3	588527	588504	0	0
T6	14442	14186	0	0
T7	60989	60807	0	0
T8	5660	5585	0	0
T9	95512	94755	0	0
T10	68812	67343	0	0
T11	13511	13179	0	0
T12	15491	15230	0	0