Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26793049

1

T1

1044

T2

6388

T3

4921

full_word

8799719

1

T1

249

T2

5109

T3

4260

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35592478	1			T1	1293		T2	11497		T3	9181
auto[TlIntgErrCmd]	96	1			T253	2		T254	8		T255	4
auto[TlIntgErrData]	105	1			T253	2		T254	8		T255	5
auto[TlIntgErrBoth]	89	1			T253	6		T254	4		T255	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10287959

1

T1

999

T2

10217

T3

7841

auto[1]

25304809

1

T1

294

T2

1280

T3

1340

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6479152	1			T1	872		T2	5600		T3	4199
auto[TlIntgErrNone]	partial	auto[1]	20313626	1			T1	172		T2	788		T3	722
auto[TlIntgErrNone]	full_word	auto[0]	3808685	1			T1	127		T2	4617		T3	3642
auto[TlIntgErrNone]	full_word	auto[1]	4991015	1			T1	122		T2	492		T3	618
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T253	1		T254	2		T255	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T253	1		T254	5		T255	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T344	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T254	1		T345	1		T257	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T254	1		T255	1		T339	1
auto[TlIntgErrData]	partial	auto[1]	58	1			T253	2		T254	5		T255	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T346	1		T345	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T254	2		T343	2		T342	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T253	5		T254	1		T255	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T254	2		T339	2		T341	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T254	1		T339	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T253	1		T347	1		T348	1