Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.40	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	483604379	8582973	0	0
check_regwen_rd_A	483604379	1920	0	0
check_timeout_rd_A	483604379	1491	0	0
check_trigger_regwen_rd_A	483604379	2047	0	0
consistency_check_period_rd_A	483604379	2006	0	0
creator_sw_cfg_read_lock_rd_A	483604379	1369	0	0
direct_access_address_rd_A	483604379	1201	0	0
direct_access_wdata_0_rd_A	483604379	926	0	0
direct_access_wdata_1_rd_A	483604379	843	0	0
integrity_check_period_rd_A	483604379	1963	0	0
intr_enable_rd_A	483604379	3089	0	0
owner_sw_cfg_read_lock_rd_A	483604379	1315	0	0
rot_creator_auth_codesign_read_lock_rd_A	483604379	1349	0	0
rot_creator_auth_state_read_lock_rd_A	483604379	1372	0	0
vendor_test_read_lock_rd_A	483604379	1356	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	8582973	0	0
T7	346519	97537	0	0
T13	904801	160606	0	0
T14	551760	101531	0	0
T15	131685	0	0	0
T18	0	88078	0	0
T19	0	105763	0	0
T20	0	137228	0	0
T68	18933	0	0	0
T72	12470	0	0	0
T78	15103	0	0	0
T95	53859	0	0	0
T218	6145	0	0	0
T219	0	26218	0	0
T234	0	319486	0	0
T259	0	120917	0	0
T260	0	185323	0	0
T261	10074	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1920	0	0
T51	8913	0	0	0
T76	0	116	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	25	0	0
T236	0	56	0	0
T239	18380	0	0	0
T243	0	77	0	0
T244	0	126	0	0
T264	0	46	0	0
T314	0	30	0	0
T318	0	48	0	0
T319	0	167	0	0
T320	0	90	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1491	0	0
T51	8913	0	0	0
T76	0	90	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	35	0	0
T236	0	25	0	0
T239	18380	0	0	0
T243	0	115	0	0
T244	0	125	0	0
T264	0	73	0	0
T314	0	103	0	0
T318	0	48	0	0
T319	0	222	0	0
T320	0	136	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	2047	0	0
T51	8913	0	0	0
T76	0	88	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	40	0	0
T236	0	48	0	0
T239	18380	0	0	0
T243	0	64	0	0
T244	0	147	0	0
T264	0	73	0	0
T314	0	55	0	0
T318	0	23	0	0
T319	0	210	0	0
T320	0	139	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	2006	0	0
T51	8913	0	0	0
T76	0	74	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	56	0	0
T236	0	40	0	0
T239	18380	0	0	0
T243	0	74	0	0
T244	0	169	0	0
T264	0	65	0	0
T314	0	53	0	0
T318	0	64	0	0
T319	0	204	0	0
T320	0	101	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1369	0	0
T51	8913	0	0	0
T76	0	100	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	30	0	0
T236	0	22	0	0
T239	18380	0	0	0
T243	0	130	0	0
T244	0	129	0	0
T264	0	103	0	0
T314	0	68	0	0
T318	0	41	0	0
T319	0	111	0	0
T320	0	80	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1201	0	0
T51	8913	0	0	0
T76	0	81	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	65	0	0
T236	0	52	0	0
T239	18380	0	0	0
T243	0	107	0	0
T244	0	117	0	0
T264	0	60	0	0
T314	0	67	0	0
T318	0	30	0	0
T319	0	166	0	0
T320	0	98	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	926	0	0
T51	8913	0	0	0
T76	0	62	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	35	0	0
T236	0	16	0	0
T239	18380	0	0	0
T243	0	86	0	0
T244	0	120	0	0
T264	0	20	0	0
T314	0	45	0	0
T318	0	18	0	0
T319	0	200	0	0
T320	0	92	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	843	0	0
T51	8913	0	0	0
T76	0	54	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	31	0	0
T236	0	53	0	0
T239	18380	0	0	0
T243	0	50	0	0
T244	0	114	0	0
T264	0	58	0	0
T314	0	62	0	0
T318	0	6	0	0
T319	0	134	0	0
T320	0	55	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1963	0	0
T51	8913	0	0	0
T76	0	55	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	59	0	0
T236	0	47	0	0
T239	18380	0	0	0
T243	0	74	0	0
T244	0	126	0	0
T264	0	51	0	0
T314	0	80	0	0
T318	0	42	0	0
T319	0	180	0	0
T320	0	92	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	3089	0	0
T6	113689	35	0	0
T50	11616	0	0	0
T99	0	66	0	0
T109	27929	0	0	0
T110	13504	0	0	0
T111	22654	0	0	0
T163	9710	0	0	0
T196	24299	0	0	0
T197	24883	0	0	0
T211	94187	0	0	0
T219	0	34	0	0
T231	0	20	0	0
T240	0	29	0	0
T243	0	101	0	0
T244	0	127	0	0
T314	0	58	0	0
T318	0	9	0	0
T319	0	239	0	0
T325	12351	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1315	0	0
T51	8913	0	0	0
T76	0	74	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	55	0	0
T236	0	14	0	0
T239	18380	0	0	0
T243	0	104	0	0
T244	0	122	0	0
T264	0	74	0	0
T314	0	53	0	0
T318	0	20	0	0
T319	0	194	0	0
T320	0	125	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1349	0	0
T51	8913	0	0	0
T76	0	89	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	49	0	0
T236	0	56	0	0
T239	18380	0	0	0
T243	0	72	0	0
T244	0	120	0	0
T264	0	66	0	0
T314	0	69	0	0
T318	0	26	0	0
T319	0	200	0	0
T320	0	119	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1372	0	0
T51	8913	0	0	0
T76	0	119	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	81	0	0
T236	0	35	0	0
T239	18380	0	0	0
T243	0	85	0	0
T244	0	139	0	0
T264	0	56	0	0
T314	0	60	0	0
T318	0	27	0	0
T319	0	153	0	0
T320	0	79	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	1356	0	0
T51	8913	0	0	0
T76	0	85	0	0
T104	28186	0	0	0
T145	805176	0	0	0
T192	352469	0	0	0
T219	174270	35	0	0
T236	0	39	0	0
T239	18380	0	0	0
T243	0	117	0	0
T244	0	103	0	0
T264	0	52	0	0
T314	0	82	0	0
T318	0	27	0	0
T319	0	208	0	0
T320	0	120	0	0
T321	75309	0	0	0
T322	8732	0	0	0
T323	12359	0	0	0
T324	58326	0	0	0