Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.40	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.40	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.40	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T162,T160,T161
1	Covered	T162,T160,T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T96,T198,T199
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T28
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T10,T17,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T4,T28
CheckFailError	317	Covered	T162,T160,T161
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T2,T17,T106
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T4,T28
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T162,T160,T161
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T4,T28
NoError->CheckFailError	317	Covered	T162,T160,T161
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T28,T29,T96
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T28
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T162,T160,T161
1	0	Covered	T162,T160,T161
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	480755465	479856981	0	0
DigestKnown_A	480755465	479856981	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	480755465	8296	0	0
ErrorKnown_A	480755465	479856981	0	0
FsmStateKnown_A	480755465	479856981	0	0
InitDoneKnown_A	480755465	479856981	0	0
InitReadLocksPartition_A	480755465	98484241	0	0
InitWriteLocksPartition_A	480755465	98484241	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	480755465	479856981	0	0
OtpCmdKnown_A	480755465	479856981	0	0
OtpErrorState_A	480755465	0	0	0
OtpReqKnown_A	480755465	479856981	0	0
OtpSizeKnown_A	480755465	479856981	0	0
OtpWdataKnown_A	480755465	479856981	0	0
ReadLockPropagation_A	480755465	201142906	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	480755465	479856981	0	0
TlulRdataKnown_A	480755465	479856981	0	0
TlulReadOnReadLock_A	480755465	8209	0	0
TlulRerrorKnown_A	480755465	479856981	0	0
TlulRvalidKnown_A	480755465	479856981	0	0
WriteLockPropagation_A	480755465	2539160	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	480755465	29443603	0	0
u_state_regs_A	480755465	479856981	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	8296	0	0
T112	51924	0	0	0
T160	0	2460	0	0
T161	0	2606	0	0
T162	11359	3230	0	0
T169	64512	0	0	0
T170	18921	0	0	0
T171	42848	0	0	0
T172	14097	0	0	0
T173	22371	0	0	0
T174	35107	0	0	0
T175	58770	0	0	0
T176	77891	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	98484241	0	0
T1	10289	4203	0	0
T2	179212	89595	0	0
T3	27221	17289	0	0
T4	84418	9602	0	0
T5	51821	35751	0	0
T8	31622	261	0	0
T9	40773	145	0	0
T10	13392	5429	0	0
T11	213226	5979	0	0
T12	9007	226	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	98484241	0	0
T1	10289	4203	0	0
T2	179212	89595	0	0
T3	27221	17289	0	0
T4	84418	9602	0	0
T5	51821	35751	0	0
T8	31622	261	0	0
T9	40773	145	0	0
T10	13392	5429	0	0
T11	213226	5979	0	0
T12	9007	226	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	201142906	0	0
T2	179212	10814	0	0
T3	27221	0	0	0
T4	84418	12628	0	0
T5	51821	0	0	0
T8	31622	2922	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	0	0	0
T12	9007	1665	0	0
T17	0	60417	0	0
T28	0	5370	0	0
T29	0	3646	0	0
T67	0	8545	0	0
T69	14767	0	0	0
T105	0	41230	0	0
T106	0	21208	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	8209	0	0
T2	179212	21	0	0
T3	27221	12	0	0
T4	84418	15	0	0
T5	51821	5	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	1	0	0
T12	9007	0	0	0
T17	0	42	0	0
T28	0	7	0	0
T67	0	10	0	0
T69	14767	0	0	0
T105	0	8	0	0
T116	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	2539160	0	0
T4	84418	4896	0	0
T5	51821	0	0	0
T6	0	92125	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	0	0	0
T12	9007	0	0	0
T16	3953	0	0	0
T17	0	23408	0	0
T29	0	2999	0	0
T36	35797	0	0	0
T69	14767	0	0	0
T95	0	1838	0	0
T96	0	12337	0	0
T97	0	7806	0	0
T99	0	71038	0	0
T100	0	1778	0	0
T103	0	14541	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	29443603	0	0
T1	10289	3000	0	0
T2	179212	65149	0	0
T3	27221	0	0	0
T4	84418	70445	0	0
T5	51821	0	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	0	0	0
T12	9007	0	0	0
T17	0	218823	0	0
T28	0	30877	0	0
T29	0	52571	0	0
T69	0	2346	0	0
T70	0	2379	0	0
T105	0	2650	0	0
T106	0	2479	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T163,T164

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T67,T108

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T160
1	Covered	T78,T160

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T28,T17

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T28,T17

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T96,T198,T199
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T166,T177,T178
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T28,T67
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T154,T155,T200
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T10,T17,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T28,T67
CheckFailError	317	Covered	T78,T160
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T1,T4,T67
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T17,T105,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T28,T67
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T160
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T108,T163
MacroEccCorrError->NoError	235	Covered	T4,T67,T40
NoError->AccessError	256	Covered	T4,T28,T67
NoError->CheckFailError	317	Covered	T78,T160
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T1,T4,T67

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T28,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T163,T164
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T166,T177,T178
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T28,T7,T96
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T28,T67
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T67,T108
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T154,T155,T200
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T160
1	0	Covered	T78,T160
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	480755465	479856981	0	0
DigestKnown_A	480755465	479856981	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	480755465	5829	0	0
ErrorKnown_A	480755465	479856981	0	0
FsmStateKnown_A	480755465	479856981	0	0
InitDoneKnown_A	480755465	479856981	0	0
InitReadLocksPartition_A	480755465	98671511	0	0
InitWriteLocksPartition_A	480755465	98671511	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	480755465	479856981	0	0
OtpCmdKnown_A	480755465	479856981	0	0
OtpErrorState_A	480755465	63	0	0
OtpReqKnown_A	480755465	479856981	0	0
OtpSizeKnown_A	480755465	479856981	0	0
OtpWdataKnown_A	480755465	479856981	0	0
ReadLockPropagation_A	480755465	199403494	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	480755465	479856981	0	0
TlulRdataKnown_A	480755465	479856981	0	0
TlulReadOnReadLock_A	480755465	8704	0	0
TlulRerrorKnown_A	480755465	479856981	0	0
TlulRvalidKnown_A	480755465	479856981	0	0
WriteLockPropagation_A	480755465	2355257	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	480755465	28914674	0	0
u_state_regs_A	480755465	479856981	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	5829	0	0
T13	904801	0	0	0
T14	551760	0	0	0
T45	9565	0	0	0
T78	15103	3369	0	0
T96	567585	0	0	0
T97	864581	0	0	0
T160	0	2460	0	0
T165	51026	0	0	0
T166	8638	0	0	0
T167	4691	0	0	0
T168	44929	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	98671511	0	0
T1	10289	4237	0	0
T2	179212	89884	0	0
T3	27221	17323	0	0
T4	84418	9857	0	0
T5	51821	35785	0	0
T8	31622	346	0	0
T9	40773	179	0	0
T10	13392	5463	0	0
T11	213226	6081	0	0
T12	9007	260	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	98671511	0	0
T1	10289	4237	0	0
T2	179212	89884	0	0
T3	27221	17323	0	0
T4	84418	9857	0	0
T5	51821	35785	0	0
T8	31622	346	0	0
T9	40773	179	0	0
T10	13392	5463	0	0
T11	213226	6081	0	0
T12	9007	260	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	63	0	0
T73	13553	0	0	0
T98	45963	0	0	0
T99	137795	0	0	0
T100	58762	0	0	0
T102	48265	0	0	0
T154	0	1	0	0
T164	12448	0	0	0
T166	8638	1	0	0
T168	44929	0	0	0
T177	11048	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T187	0	1	0	0
T191	14515	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	199403494	0	0
T2	179212	4322	0	0
T3	27221	0	0	0
T4	84418	9672	0	0
T5	51821	0	0	0
T8	31622	2910	0	0
T9	40773	0	0	0
T10	13392	326	0	0
T11	213226	0	0	0
T12	9007	1655	0	0
T17	0	47463	0	0
T28	0	9224	0	0
T67	0	8539	0	0
T69	14767	0	0	0
T105	0	41226	0	0
T106	0	21557	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	8704	0	0
T2	179212	16	0	0
T3	27221	16	0	0
T4	84418	18	0	0
T5	51821	10	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	1	0	0
T12	9007	0	0	0
T17	0	31	0	0
T28	0	13	0	0
T67	0	8	0	0
T69	14767	0	0	0
T105	0	7	0	0
T116	0	17	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	2355257	0	0
T4	84418	4896	0	0
T5	51821	0	0	0
T6	0	89704	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	0	0	0
T12	9007	0	0	0
T16	3953	0	0	0
T17	0	17055	0	0
T28	0	1865	0	0
T29	0	3949	0	0
T36	35797	0	0	0
T69	14767	0	0	0
T95	0	7815	0	0
T96	0	11408	0	0
T97	0	43112	0	0
T99	0	53835	0	0
T102	0	1553	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	28914674	0	0
T4	84418	70207	0	0
T5	51821	0	0	0
T6	0	590324	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	0	0	0
T12	9007	0	0	0
T16	3953	0	0	0
T17	0	219690	0	0
T28	0	30741	0	0
T29	0	52350	0	0
T36	35797	0	0	0
T69	14767	0	0	0
T105	0	2633	0	0
T106	0	2462	0	0
T108	0	5336	0	0
T196	0	5867	0	0
T197	0	2632	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T45,T159,T71

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T4,T67

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T160,T161
1	Covered	T78,T160,T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T69

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T69

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T96,T198,T199
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T69,T70,T163
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T28
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T201,T155,T202
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T10,T17,T78
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T28
CheckFailError	317	Covered	T78,T160,T161
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T2,T4,T67
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T2,T105,T106
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T28
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T160,T161
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T108,T45
MacroEccCorrError->NoError	235	Covered	T4,T67,T203
NoError->AccessError	256	Covered	T2,T4,T28
NoError->CheckFailError	317	Covered	T78,T160,T161
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T2,T4,T67

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T69
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T45,T159,T71
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T163
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T29,T96,T97
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T28
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T4,T67
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T201,T155,T202
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T160,T161
1	0	Covered	T78,T160,T161
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	480755465	479856981	0	0
DigestKnown_A	480755465	479856981	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	480755465	8435	0	0
ErrorKnown_A	480755465	479856981	0	0
FsmStateKnown_A	480755465	479856981	0	0
InitDoneKnown_A	480755465	479856981	0	0
InitReadLocksPartition_A	480755465	98857679	0	0
InitWriteLocksPartition_A	480755465	98857679	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	480755465	479856981	0	0
OtpCmdKnown_A	480755465	479856981	0	0
OtpErrorState_A	480755465	54	0	0
OtpReqKnown_A	480755465	479856981	0	0
OtpSizeKnown_A	480755465	479856981	0	0
OtpWdataKnown_A	480755465	479856981	0	0
ReadLockPropagation_A	480755465	197024067	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	480755465	479856981	0	0
TlulRdataKnown_A	480755465	479856981	0	0
TlulReadOnReadLock_A	480755465	8832	0	0
TlulRerrorKnown_A	480755465	479856981	0	0
TlulRvalidKnown_A	480755465	479856981	0	0
WriteLockPropagation_A	480755465	1294961	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	480755465	16824241	0	0
u_state_regs_A	480755465	479856981	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	8435	0	0
T13	904801	0	0	0
T14	551760	0	0	0
T45	9565	0	0	0
T78	15103	3369	0	0
T96	567585	0	0	0
T97	864581	0	0	0
T160	0	2460	0	0
T161	0	2606	0	0
T165	51026	0	0	0
T166	8638	0	0	0
T167	4691	0	0	0
T168	44929	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	98857679	0	0
T1	10289	4271	0	0
T2	179212	90173	0	0
T3	27221	17357	0	0
T4	84418	10112	0	0
T5	51821	35819	0	0
T8	31622	431	0	0
T9	40773	213	0	0
T10	13392	5497	0	0
T11	213226	6183	0	0
T12	9007	294	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	98857679	0	0
T1	10289	4271	0	0
T2	179212	90173	0	0
T3	27221	17357	0	0
T4	84418	10112	0	0
T5	51821	35819	0	0
T8	31622	431	0	0
T9	40773	213	0	0
T10	13392	5497	0	0
T11	213226	6183	0	0
T12	9007	294	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	54	0	0
T16	3953	0	0	0
T17	503246	0	0	0
T28	48634	0	0	0
T36	35797	0	0	0
T67	65656	0	0	0
T69	14767	1	0	0
T70	7436	1	0	0
T92	0	1	0	0
T105	46923	0	0	0
T106	29325	0	0	0
T116	19122	0	0	0
T163	0	1	0	0
T183	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	197024067	0	0
T2	179212	10808	0	0
T3	27221	0	0	0
T4	84418	11583	0	0
T5	51821	0	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	324	0	0
T11	213226	0	0	0
T12	9007	1653	0	0
T17	0	56595	0	0
T28	0	7236	0	0
T29	0	5996	0	0
T67	0	5290	0	0
T69	14767	0	0	0
T105	0	41216	0	0
T106	0	21555	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	8832	0	0
T2	179212	16	0	0
T3	27221	15	0	0
T4	84418	17	0	0
T5	51821	6	0	0
T8	31622	0	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	1	0	0
T12	9007	0	0	0
T17	0	41	0	0
T28	0	10	0	0
T67	0	9	0	0
T69	14767	0	0	0
T105	0	19	0	0
T116	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	1294961	0	0
T6	0	70340	0	0
T17	503246	10732	0	0
T28	48634	4459	0	0
T29	64922	0	0	0
T67	65656	0	0	0
T70	7436	0	0	0
T96	0	7690	0	0
T97	0	5228	0	0
T99	0	46972	0	0
T103	0	1992	0	0
T105	46923	0	0	0
T106	29325	0	0	0
T107	25465	0	0	0
T108	61082	0	0	0
T116	19122	0	0	0
T193	0	9208	0	0
T194	0	4433	0	0
T195	0	6323	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	16824241	0	0
T2	179212	64911	0	0
T3	27221	0	0	0
T4	84418	0	0	0
T5	51821	0	0	0
T6	0	476022	0	0
T8	31622	6284	0	0
T9	40773	0	0	0
T10	13392	0	0	0
T11	213226	0	0	0
T12	9007	0	0	0
T17	0	171793	0	0
T28	0	40190	0	0
T69	14767	2324	0	0
T70	0	2357	0	0
T108	0	5319	0	0
T163	0	3010	0	0
T197	0	2615	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0