Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.36	75.00	93.07			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2.wr_en_data_arb	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3.wr_en_data_arb	0.00	0.00
tb.dut.u_reg_core.u_intr_state_otp_operation_done.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_intr_state_otp_error.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_intr_enable_otp_operation_done.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_intr_enable_otp_error.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_direct_access_address.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_direct_access_wdata_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_direct_access_wdata_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_check_trigger_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_check_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_check_timeout.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_integrity_check_period.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_consistency_check_period.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_vendor_test_read_lock.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_creator_sw_cfg_read_lock.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_owner_sw_cfg_read_lock.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_rot_creator_auth_codesign_read_lock.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg_core.u_rot_creator_auth_state_read_lock.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3.wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=3,SwAccess=3,Mubi=0 + DW=10,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_intr_state_otp_operation_done.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_intr_state_otp_error.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=11,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=6,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_otp_operation_done.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_otp_error.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_direct_access_address.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_direct_access_wdata_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_direct_access_wdata_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_check_timeout.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_integrity_check_period.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_consistency_check_period.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_check_trigger_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_check_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_vendor_test_read_lock.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_creator_sw_cfg_read_lock.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_owner_sw_cfg_read_lock.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_rot_creator_auth_codesign_read_lock.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_rot_creator_auth_state_read_lock.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=3,SwAccess=1,Mubi=0 + DW=6,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=3,Mubi=0 + DW=10,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T6,T7

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T17,T6,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_state_otp_operation_done.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_state_otp_error.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_otp_operation_done.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_otp_error.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=11,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_direct_access_address.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field4.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T17,T6,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3.wr_en_data_arb

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T6,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_check_trigger_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_check_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_vendor_test_read_lock.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_creator_sw_cfg_read_lock.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_owner_sw_cfg_read_lock.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_rot_creator_auth_codesign_read_lock.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_rot_creator_auth_state_read_lock.wr_en_data_arb

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_direct_access_wdata_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_direct_access_wdata_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_check_timeout.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_integrity_check_period.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_consistency_check_period.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=6,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T6,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T6,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T6,T7

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3