Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

28325418

1

T1

1260

T2

7470

T3

1113

full_word

9294667

1

T1

215

T2

2689

T3

260

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	37619785	1			T1	1475		T2	10159		T3	1373
auto[TlIntgErrCmd]	113	1			T274	6		T275	9		T276	9
auto[TlIntgErrData]	95	1			T274	8		T275	3		T276	8
auto[TlIntgErrBoth]	92	1			T274	6		T275	8		T276	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10643090

1

T1

1237

T2

9436

T3

1085

auto[1]

26976995

1

T1

238

T2

723

T3

288

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6674155	1			T1	1122		T2	7009		T3	944
auto[TlIntgErrNone]	partial	auto[1]	21650984	1			T1	138		T2	461		T3	169
auto[TlIntgErrNone]	full_word	auto[0]	3968796	1			T1	115		T2	2427		T3	141
auto[TlIntgErrNone]	full_word	auto[1]	5325850	1			T1	100		T2	262		T3	119
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T274	2		T275	2		T276	5
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T274	4		T275	6		T276	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T275	1		T280	1		T364	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T276	1		T365	1		T362	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T274	3		T275	2		T276	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T274	2		T275	1		T276	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T274	2		T281	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T274	1		T359	1		T360	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T274	4		T275	4		T276	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T274	1		T275	3		T276	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T274	1		T275	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T282	1		T366	1		-	-