Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.21 98.59 85.95 92.31 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter_sram 98.85 100.00 95.41 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter_sram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.85 100.00 95.41 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.13 89.71 93.03 89.77 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.82 97.40 96.15 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 91.36 95.00 87.10 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 92.37 95.00 89.47 85.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 91.36 95.00 87.10 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL717098.59
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12433100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS2668787.50
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43611100.00
CONT_ASSIGN43711100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN47011100.00
ALWAYS48833100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 unreachable
MISSING_ELSE
133 1 1
138 1 1
145 1 1
150 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 0 1
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
436 1 1
437 1 1
438 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 1 1
463 1 1
470 1 1
488 1 1
489 1 1
490 1 1
494 1 1
497 1 1
502 1 1
507 1 1


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions12110485.95
Logical12110485.95
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T9,T11
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000CoveredT4,T7,T13
100000Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T7,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T12
11CoveredT1,T2,T3

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T7,T13
1CoveredT1,T2,T3

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T13
10CoveredT2,T4,T5

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT4,T7,T13
1110Not Covered
1111CoveredT1,T2,T3

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T5
11CoveredT1,T2,T3

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT4,T7,T13
10CoveredT1,T2,T3
11Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T7,T13
111CoveredT4,T7,T13

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T13

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T7,T13

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T15,T243
110Not Covered
111CoveredT1,T2,T3

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T13
10CoveredT1,T2,T3

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT4,T7,T13
111CoveredT1,T2,T3

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T7,T13

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T13

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT4,T7,T13
10CoveredT1,T2,T3
11CoveredT4,T7,T13

 LINE       438
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT4,T7,T13
11CoveredT1,T2,T3

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T7,T13
11CoveredT1,T2,T3

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 24 92.31
TERNARY 138 2 2 100.00
TERNARY 328 2 2 100.00
TERNARY 334 3 2 66.67
TERNARY 379 2 2 100.00
TERNARY 502 2 2 100.00
IF 124 2 2 100.00
IF 268 4 3 75.00
IF 288 3 3 100.00
IF 349 2 2 100.00
IF 412 2 2 100.00
IF 424 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 328 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 334 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 502 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 124 if ((!rst_ni)) -2-: 126 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (reqfifo_rvalid) -2-: 269 if (reqfifo_rdata.error) -3-: 272 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T4,T7,T13
1 0 1 Covered T1,T2,T3
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 288 if (reqfifo_rvalid) -2-: 289 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T4,T7,T13
0 - Covered T1,T2,T3


LineNo. Expression -1-: 349 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 412 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 512931934 512068706 0 0
DataIntgOptions_A 1152 1152 0 0
ReqOutKnown_A 512931934 512068706 0 0
SramDwHasByteGranularity_A 1152 1152 0 0
SramDwIsMultipleOfTlulWidth_A 1152 1152 0 0
TlOutKnownIfFifoKnown_A 512931934 512068706 0 0
TlOutValidKnown_A 512931934 512068706 0 0
WdataOutKnown_A 512931934 512068706 0 0
WeOutKnown_A 512931934 512068706 0 0
WmaskOutKnown_A 512931934 512068706 0 0
adapterNoReadOrWrite 1152 1152 0 0
rvalidHighReqFifoEmpty 512931934 103031 0 0
rvalidHighWhenRspFifoFull 512931934 103031 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 103031 0 0
T1 11900 16 0 0
T2 72245 50 0 0
T3 11961 14 0 0
T4 447757 144 0 0
T5 43899 10 0 0
T8 14358 25 0 0
T9 14944 18 0 0
T10 414343 594 0 0
T11 5211 0 0 0
T12 79060 39 0 0
T26 0 17 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 103031 0 0
T1 11900 16 0 0
T2 72245 50 0 0
T3 11961 14 0 0
T4 447757 144 0 0
T5 43899 10 0 0
T8 14358 25 0 0
T9 14944 18 0 0
T10 414343 594 0 0
T11 5211 0 0 0
T12 79060 39 0 0
T26 0 17 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL7070100.00
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12433100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS26677100.00
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43611100.00
CONT_ASSIGN43711100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN47011100.00
ALWAYS48833100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 unreachable
MISSING_ELSE
133 1 1
138 1 1
145 1 1
150 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 excluded
Exclude Annotation: VC_COV_UNR
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
436 1 1
437 1 1
438 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 1 1
463 1 1
470 1 1
488 1 1
489 1 1
490 1 1
494 1 1
497 1 1
502 1 1
507 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram
TotalCoveredPercent
Conditions10910495.41
Logical10910495.41
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTestsExclude Annotation
000CoveredT1,T2,T3
001Excluded VC_COV_UNR
010Unreachable
100Unreachable

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T9,T11
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTestsExclude Annotation
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000CoveredT4,T7,T13
100000Excluded VC_COV_UNR

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T7,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T12
11CoveredT1,T2,T3

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT1,T2,T3

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T7,T13
1CoveredT1,T2,T3

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T13
10CoveredT2,T4,T5

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTestsExclude Annotation
0111Excluded VC_COV_UNR
1011Excluded VC_COV_UNR
1101CoveredT4,T7,T13
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T5
11CoveredT1,T2,T3

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTestsExclude Annotation
01CoveredT4,T7,T13
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T7,T13
111CoveredT4,T7,T13

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T13

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T7,T13

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T15,T243
110Not Covered
111CoveredT1,T2,T3

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T13
10CoveredT1,T2,T3

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT4,T7,T13
111CoveredT1,T2,T3

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T7,T13

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T13

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT4,T7,T13
10CoveredT1,T2,T3
11CoveredT4,T7,T13

 LINE       438
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTestsExclude Annotation
01Excluded vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR
10CoveredT4,T7,T13
11CoveredT1,T2,T3

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T7,T13
11CoveredT1,T2,T3

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 138 2 2 100.00
TERNARY 328 2 2 100.00
TERNARY 334 2 2 100.00
TERNARY 379 2 2 100.00
TERNARY 502 2 2 100.00
IF 124 2 2 100.00
IF 268 3 3 100.00
IF 288 3 3 100.00
IF 349 2 2 100.00
IF 412 2 2 100.00
IF 424 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 328 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 334 (vld_rd_rsp) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Excluded VC_COV_UNR
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 502 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 124 if ((!rst_ni)) -2-: 126 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (reqfifo_rvalid) -2-: 269 if (reqfifo_rdata.error) -3-: 272 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTestsExclude Annotation
1 1 - Covered T4,T7,T13
1 0 1 Covered T1,T2,T3
1 0 0 Excluded VC_COV_UNR
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 288 if (reqfifo_rvalid) -2-: 289 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T4,T7,T13
0 - Covered T1,T2,T3


LineNo. Expression -1-: 349 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 412 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 512931934 512068706 0 0
DataIntgOptions_A 1152 1152 0 0
ReqOutKnown_A 512931934 512068706 0 0
SramDwHasByteGranularity_A 1152 1152 0 0
SramDwIsMultipleOfTlulWidth_A 1152 1152 0 0
TlOutKnownIfFifoKnown_A 512931934 512068706 0 0
TlOutValidKnown_A 512931934 512068706 0 0
WdataOutKnown_A 512931934 512068706 0 0
WeOutKnown_A 512931934 512068706 0 0
WmaskOutKnown_A 512931934 512068706 0 0
adapterNoReadOrWrite 1152 1152 0 0
rvalidHighReqFifoEmpty 512931934 103031 0 0
rvalidHighWhenRspFifoFull 512931934 103031 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 512068706 0 0
T1 11900 11640 0 0
T2 72245 71111 0 0
T3 11961 11687 0 0
T4 447757 447742 0 0
T5 43899 43095 0 0
T8 14358 14100 0 0
T9 14944 14674 0 0
T10 414343 407956 0 0
T11 5211 5154 0 0
T12 79060 78403 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1152 1152 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 103031 0 0
T1 11900 16 0 0
T2 72245 50 0 0
T3 11961 14 0 0
T4 447757 144 0 0
T5 43899 10 0 0
T8 14358 25 0 0
T9 14944 18 0 0
T10 414343 594 0 0
T11 5211 0 0 0
T12 79060 39 0 0
T26 0 17 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 512931934 103031 0 0
T1 11900 16 0 0
T2 72245 50 0 0
T3 11961 14 0 0
T4 447757 144 0 0
T5 43899 10 0 0
T8 14358 25 0 0
T9 14944 18 0 0
T10 414343 594 0 0
T11 5211 0 0 0
T12 79060 39 0 0
T26 0 17 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%