Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	515914450	9203021	0	0
check_regwen_rd_A	515914450	3289	0	0
check_timeout_rd_A	515914450	3066	0	0
check_trigger_regwen_rd_A	515914450	3190	0	0
consistency_check_period_rd_A	515914450	3331	0	0
creator_sw_cfg_read_lock_rd_A	515914450	3084	0	0
direct_access_address_rd_A	515914450	2485	0	0
direct_access_wdata_0_rd_A	515914450	1670	0	0
direct_access_wdata_1_rd_A	515914450	1791	0	0
integrity_check_period_rd_A	515914450	3281	0	0
intr_enable_rd_A	515914450	3498	0	0
owner_sw_cfg_read_lock_rd_A	515914450	2614	0	0
rot_creator_auth_codesign_read_lock_rd_A	515914450	3062	0	0
rot_creator_auth_state_read_lock_rd_A	515914450	2601	0	0
vendor_test_read_lock_rd_A	515914450	2822	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	9203021	0	0
T4	447757	87042	0	0
T5	43899	0	0	0
T7	0	44276	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T13	0	47678	0	0
T15	0	91358	0	0
T16	0	21547	0	0
T26	84072	0	0	0
T34	0	129457	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T125	0	102501	0	0
T132	0	43298	0	0
T206	0	78405	0	0
T283	0	109165	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3289	0	0
T4	447757	72	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	111	0	0
T18	0	77	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	89	0	0
T292	0	40	0	0
T342	0	42	0	0
T343	0	182	0	0
T344	0	157	0	0
T345	0	154	0	0
T346	0	76	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3066	0	0
T4	447757	55	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	133	0	0
T18	0	72	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	100	0	0
T292	0	88	0	0
T342	0	39	0	0
T343	0	177	0	0
T344	0	186	0	0
T345	0	146	0	0
T346	0	72	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3190	0	0
T4	447757	59	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	95	0	0
T18	0	82	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	51	0	0
T292	0	95	0	0
T342	0	50	0	0
T343	0	181	0	0
T344	0	139	0	0
T345	0	135	0	0
T346	0	81	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3331	0	0
T4	447757	80	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	178	0	0
T18	0	68	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	72	0	0
T292	0	63	0	0
T342	0	53	0	0
T343	0	164	0	0
T344	0	98	0	0
T345	0	159	0	0
T346	0	42	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3084	0	0
T4	447757	55	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	137	0	0
T18	0	53	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	104	0	0
T292	0	58	0	0
T342	0	56	0	0
T343	0	186	0	0
T344	0	141	0	0
T345	0	117	0	0
T346	0	86	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	2485	0	0
T4	447757	69	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	107	0	0
T18	0	90	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	99	0	0
T292	0	39	0	0
T342	0	68	0	0
T343	0	189	0	0
T344	0	170	0	0
T345	0	210	0	0
T346	0	78	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	1670	0	0
T4	447757	35	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	107	0	0
T18	0	28	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	47	0	0
T292	0	58	0	0
T342	0	52	0	0
T343	0	147	0	0
T344	0	112	0	0
T345	0	105	0	0
T346	0	52	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	1791	0	0
T4	447757	34	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	131	0	0
T18	0	45	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	56	0	0
T292	0	44	0	0
T342	0	40	0	0
T343	0	161	0	0
T344	0	95	0	0
T345	0	139	0	0
T346	0	50	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3281	0	0
T4	447757	52	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	113	0	0
T18	0	85	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	73	0	0
T292	0	60	0	0
T342	0	58	0	0
T343	0	154	0	0
T344	0	116	0	0
T345	0	155	0	0
T346	0	76	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3498	0	0
T4	447757	62	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	130	0	0
T18	0	85	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T119	0	20	0	0
T210	0	18	0	0
T243	0	54	0	0
T342	0	68	0	0
T343	0	138	0	0
T344	0	167	0	0
T345	0	93	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	2614	0	0
T4	447757	49	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	150	0	0
T18	0	83	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	62	0	0
T292	0	53	0	0
T342	0	62	0	0
T343	0	172	0	0
T344	0	120	0	0
T345	0	153	0	0
T346	0	74	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	3062	0	0
T4	447757	82	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	119	0	0
T18	0	131	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	79	0	0
T292	0	26	0	0
T342	0	58	0	0
T343	0	233	0	0
T344	0	104	0	0
T345	0	116	0	0
T346	0	93	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	2601	0	0
T4	447757	79	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	81	0	0
T18	0	77	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	74	0	0
T292	0	57	0	0
T342	0	66	0	0
T343	0	150	0	0
T344	0	151	0	0
T345	0	149	0	0
T346	0	59	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515914450	2822	0	0
T4	447757	59	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	0	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T15	0	87	0	0
T18	0	74	0	0
T26	84072	0	0	0
T92	84928	0	0	0
T99	11821	0	0	0
T243	0	93	0	0
T292	0	80	0	0
T342	0	50	0	0
T343	0	226	0	0
T344	0	159	0	0
T345	0	101	0	0
T346	0	80	0	0