Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T159,T158,T160
1	Covered	T159,T158,T160

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T4
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T213
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T108,T164,T209
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T10
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T4,T10
CheckFailError	317	Covered	T159,T158,T160
FsmStateError	289	Covered	T1,T3,T4
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T4,T6,T7
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T4,T10
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T159,T158,T160
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T3,T4
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T4,T10
NoError->CheckFailError	317	Covered	T159,T158,T160
NoError->FsmStateError	289	Covered	T1,T3,T4
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T13,T96,T98
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T10,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T10,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T159,T158,T160
1	0	Covered	T159,T158,T160
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	512931934	512068706	0	0
DigestKnown_A	512931934	512068706	0	0
DigestOffsetMustBeRepresentable_A	1152	1152	0	0
EccErrorState_A	512931934	10783	0	0
ErrorKnown_A	512931934	512068706	0	0
FsmStateKnown_A	512931934	512068706	0	0
InitDoneKnown_A	512931934	512068706	0	0
InitReadLocksPartition_A	512931934	110441726	0	0
InitWriteLocksPartition_A	512931934	110441726	0	0
OffsetMustBeBlockAligned_A	1152	1152	0	0
OtpAddrKnown_A	512931934	512068706	0	0
OtpCmdKnown_A	512931934	512068706	0	0
OtpErrorState_A	512931934	0	0	0
OtpReqKnown_A	512931934	512068706	0	0
OtpSizeKnown_A	512931934	512068706	0	0
OtpWdataKnown_A	512931934	512068706	0	0
ReadLockPropagation_A	512931934	230396187	0	0
SizeMustBeBlockAligned_A	1152	1152	0	0
TlulGntKnown_A	512931934	512068706	0	0
TlulRdataKnown_A	512931934	512068706	0	0
TlulReadOnReadLock_A	512931934	8701	0	0
TlulRerrorKnown_A	512931934	512068706	0	0
TlulRvalidKnown_A	512931934	512068706	0	0
WriteLockPropagation_A	512931934	2349690	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	512931934	27726722	0	0
u_state_regs_A	512931934	512068706	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	10783	0	0
T158	15257	3241	0	0
T159	13721	2533	0	0
T160	0	2146	0	0
T170	0	2863	0	0
T177	221088	0	0	0
T178	22766	0	0	0
T179	13206	0	0	0
T180	41163	0	0	0
T181	13152	0	0	0
T182	13075	0	0	0
T183	21530	0	0	0
T184	12735	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	110441726	0	0
T1	11900	4328	0	0
T2	72245	902	0	0
T3	11961	3995	0	0
T4	447757	130702	0	0
T5	43899	2732	0	0
T8	14358	5864	0	0
T9	14944	2998	0	0
T10	414343	38178	0	0
T11	5211	183	0	0
T12	79060	10690	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	110441726	0	0
T1	11900	4328	0	0
T2	72245	902	0	0
T3	11961	3995	0	0
T4	447757	130702	0	0
T5	43899	2732	0	0
T8	14358	5864	0	0
T9	14944	2998	0	0
T10	414343	38178	0	0
T11	5211	183	0	0
T12	79060	10690	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	230396187	0	0
T2	72245	7381	0	0
T3	11961	0	0	0
T4	447757	178853	0	0
T5	43899	0	0	0
T6	0	62651	0	0
T7	0	981038	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	20347	0	0
T11	5211	0	0	0
T12	79060	16675	0	0
T26	84072	15937	0	0
T62	0	32187	0	0
T63	0	56842	0	0
T92	0	12313	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	8701	0	0
T2	72245	4	0	0
T3	11961	0	0	0
T4	447757	19	0	0
T5	43899	1	0	0
T6	0	12	0	0
T7	0	35	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	14	0	0
T11	5211	0	0	0
T12	79060	6	0	0
T26	84072	0	0	0
T62	0	8	0	0
T63	0	12	0	0
T92	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	2349690	0	0
T2	72245	5069	0	0
T3	11961	0	0	0
T4	447757	0	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	4497	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T14	0	9917	0	0
T26	84072	5661	0	0
T92	0	3225	0	0
T94	0	4579	0	0
T96	0	9541	0	0
T104	0	14180	0	0
T172	0	3054	0	0
T207	0	4999	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	27726722	0	0
T2	72245	65362	0	0
T3	11961	0	0	0
T4	447757	0	0	0
T5	43899	0	0	0
T8	14358	3689	0	0
T9	14944	0	0	0
T10	414343	202750	0	0
T11	5211	0	0	0
T12	79060	48739	0	0
T24	0	7751	0	0
T26	84072	72887	0	0
T63	0	120733	0	0
T92	0	76050	0	0
T93	0	56261	0	0
T151	0	11790	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T9

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T62

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T72,T73,T157
1	Covered	T72,T73,T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T26

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T26

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T4
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T108,T164,T209
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T185,T187,T189
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T10
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T186,T214,T215
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T10
CheckFailError	317	Covered	T72,T73,T157
FsmStateError	289	Covered	T1,T3,T4
MacroEccCorrError	221	Covered	T3,T5,T8
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T7,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T10
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T72,T73,T157
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T3,T5,T8
MacroEccCorrError->NoError	235	Covered	T12,T62,T151
NoError->AccessError	256	Covered	T2,T4,T10
NoError->CheckFailError	317	Covered	T72,T73,T157
NoError->FsmStateError	289	Covered	T1,T4,T5
NoError->MacroEccCorrError	221	Covered	T3,T5,T8

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T9
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T185,T187,T189
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T4,T10,T13
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T5,T12,T62
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T186,T214,T215
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T10,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T10,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T72,T73,T157
1	0	Covered	T72,T73,T157
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	512931934	512068706	0	0
DigestKnown_A	512931934	512068706	0	0
DigestOffsetMustBeRepresentable_A	1152	1152	0	0
EccErrorState_A	512931934	23958	0	0
ErrorKnown_A	512931934	512068706	0	0
FsmStateKnown_A	512931934	512068706	0	0
InitDoneKnown_A	512931934	512068706	0	0
InitReadLocksPartition_A	512931934	110625266	0	0
InitWriteLocksPartition_A	512931934	110625266	0	0
OffsetMustBeBlockAligned_A	1152	1152	0	0
OtpAddrKnown_A	512931934	512068706	0	0
OtpCmdKnown_A	512931934	512068706	0	0
OtpErrorState_A	512931934	70	0	0
OtpReqKnown_A	512931934	512068706	0	0
OtpSizeKnown_A	512931934	512068706	0	0
OtpWdataKnown_A	512931934	512068706	0	0
ReadLockPropagation_A	512931934	226318740	0	0
SizeMustBeBlockAligned_A	1152	1152	0	0
TlulGntKnown_A	512931934	512068706	0	0
TlulRdataKnown_A	512931934	512068706	0	0
TlulReadOnReadLock_A	512931934	9023	0	0
TlulRerrorKnown_A	512931934	512068706	0	0
TlulRvalidKnown_A	512931934	512068706	0	0
WriteLockPropagation_A	512931934	2555186	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	512931934	27609405	0	0
u_state_regs_A	512931934	512068706	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	23958	0	0
T72	10938	3779	0	0
T73	0	3720	0	0
T140	12503	0	0	0
T157	0	2557	0	0
T158	0	3241	0	0
T161	79003	0	0	0
T163	0	2215	0	0
T166	13912	0	0	0
T168	0	2361	0	0
T169	0	3222	0	0
T170	0	2863	0	0
T171	31728	0	0	0
T172	51294	0	0	0
T173	73083	0	0	0
T174	15622	0	0	0
T175	10813	0	0	0
T176	41766	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	110625266	0	0
T1	11900	4379	0	0
T2	72245	1157	0	0
T3	11961	4046	0	0
T4	447757	130721	0	0
T5	43899	2885	0	0
T8	14358	5898	0	0
T9	14944	3049	0	0
T10	414343	39487	0	0
T11	5211	200	0	0
T12	79060	10843	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	110625266	0	0
T1	11900	4379	0	0
T2	72245	1157	0	0
T3	11961	4046	0	0
T4	447757	130721	0	0
T5	43899	2885	0	0
T8	14358	5898	0	0
T9	14944	3049	0	0
T10	414343	39487	0	0
T11	5211	200	0	0
T12	79060	10843	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	70	0	0
T46	73016	0	0	0
T118	400506	0	0	0
T141	89186	0	0	0
T185	13166	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T198	0	1	0	0
T201	156272	0	0	0
T202	6816	0	0	0
T203	17513	0	0	0
T204	18864	0	0	0
T205	30933	0	0	0
T206	271497	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	226318740	0	0
T2	72245	7066	0	0
T3	11961	0	0	0
T4	447757	185675	0	0
T5	43899	0	0	0
T6	0	61023	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	27578	0	0
T11	5211	0	0	0
T12	79060	21842	0	0
T26	84072	13106	0	0
T62	0	35765	0	0
T63	0	40009	0	0
T92	0	9539	0	0
T99	0	2635	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	9023	0	0
T2	72245	1	0	0
T3	11961	0	0	0
T4	447757	25	0	0
T5	43899	2	0	0
T6	0	7	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	19	0	0
T11	5211	0	0	0
T12	79060	7	0	0
T26	84072	1	0	0
T62	0	9	0	0
T92	0	5	0	0
T99	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	2555186	0	0
T2	72245	7706	0	0
T3	11961	0	0	0
T4	447757	0	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	18173	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T14	0	1725	0	0
T26	84072	3632	0	0
T62	0	11918	0	0
T63	0	15569	0	0
T92	0	3519	0	0
T93	0	6521	0	0
T94	0	4579	0	0
T103	0	12929	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	27609405	0	0
T2	72245	65124	0	0
T3	11961	0	0	0
T4	447757	0	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	160534	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T14	0	127879	0	0
T26	84072	31627	0	0
T62	0	104688	0	0
T63	0	120546	0	0
T92	0	68011	0	0
T93	0	56040	0	0
T94	0	66088	0	0
T103	0	79687	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T156,T80

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T62

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T73,T148,T157
1	Covered	T73,T148,T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T101

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T101

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T4
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T108,T164,T209
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T101,T166,T185
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T10
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T161,T165,T216
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T10
CheckFailError	317	Covered	T73,T148,T157
FsmStateError	289	Covered	T1,T3,T4
MacroEccCorrError	221	Covered	T5,T12,T62
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T7,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T10
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T73,T148,T157
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T5,T151,T78
MacroEccCorrError->NoError	235	Covered	T12,T62,T151
NoError->AccessError	256	Covered	T2,T4,T10
NoError->CheckFailError	317	Covered	T73,T148,T157
NoError->FsmStateError	289	Covered	T1,T3,T4
NoError->MacroEccCorrError	221	Covered	T5,T12,T62

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T101
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T78,T156,T80
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T101,T166,T188
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T10,T13,T96
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T5,T12,T62
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T161,T165,T216
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T10,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T10,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T73,T148,T157
1	0	Covered	T73,T148,T157
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	512931934	512068706	0	0
DigestKnown_A	512931934	512068706	0	0
DigestOffsetMustBeRepresentable_A	1152	1152	0	0
EccErrorState_A	512931934	18222	0	0
ErrorKnown_A	512931934	512068706	0	0
FsmStateKnown_A	512931934	512068706	0	0
InitDoneKnown_A	512931934	512068706	0	0
InitReadLocksPartition_A	512931934	110807633	0	0
InitWriteLocksPartition_A	512931934	110807633	0	0
OffsetMustBeBlockAligned_A	1152	1152	0	0
OtpAddrKnown_A	512931934	512068706	0	0
OtpCmdKnown_A	512931934	512068706	0	0
OtpErrorState_A	512931934	45	0	0
OtpReqKnown_A	512931934	512068706	0	0
OtpSizeKnown_A	512931934	512068706	0	0
OtpWdataKnown_A	512931934	512068706	0	0
ReadLockPropagation_A	512931934	233566074	0	0
SizeMustBeBlockAligned_A	1152	1152	0	0
TlulGntKnown_A	512931934	512068706	0	0
TlulRdataKnown_A	512931934	512068706	0	0
TlulReadOnReadLock_A	512931934	9085	0	0
TlulRerrorKnown_A	512931934	512068706	0	0
TlulRvalidKnown_A	512931934	512068706	0	0
WriteLockPropagation_A	512931934	1335962	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	512931934	16714523	0	0
u_state_regs_A	512931934	512068706	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	18222	0	0
T53	66609	0	0	0
T69	77324	0	0	0
T73	16351	3720	0	0
T148	0	3829	0	0
T157	0	2557	0	0
T159	0	2533	0	0
T168	0	2361	0	0
T169	0	3222	0	0
T188	10039	0	0	0
T217	88231	0	0	0
T218	18116	0	0	0
T219	8517	0	0	0
T220	548739	0	0	0
T221	314619	0	0	0
T222	25135	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	110807633	0	0
T1	11900	4430	0	0
T2	72245	1412	0	0
T3	11961	4097	0	0
T4	447757	130740	0	0
T5	43899	3038	0	0
T8	14358	5932	0	0
T9	14944	3100	0	0
T10	414343	40796	0	0
T11	5211	217	0	0
T12	79060	10996	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	110807633	0	0
T1	11900	4430	0	0
T2	72245	1412	0	0
T3	11961	4097	0	0
T4	447757	130740	0	0
T5	43899	3038	0	0
T8	14358	5932	0	0
T9	14944	3100	0	0
T10	414343	40796	0	0
T11	5211	217	0	0
T12	79060	10996	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	45	0	0
T6	68806	0	0	0
T7	139537	0	0	0
T43	13284	0	0	0
T44	12357	0	0	0
T62	122429	0	0	0
T63	172799	0	0	0
T101	14672	1	0	0
T102	5516	0	0	0
T105	12177	0	0	0
T106	14693	0	0	0
T161	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T188	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T197	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	233566074	0	0
T2	72245	5531	0	0
T3	11961	0	0	0
T4	447757	183632	0	0
T5	43899	0	0	0
T6	0	62639	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	26724	0	0
T11	5211	0	0	0
T12	79060	17986	0	0
T26	84072	22007	0	0
T62	0	33637	0	0
T63	0	48340	0	0
T92	0	10800	0	0
T99	0	2825	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	9085	0	0
T2	72245	2	0	0
T3	11961	0	0	0
T4	447757	32	0	0
T5	43899	1	0	0
T6	0	3	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	18	0	0
T11	5211	0	0	0
T12	79060	3	0	0
T26	84072	1	0	0
T62	0	5	0	0
T92	0	8	0	0
T99	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	1335962	0	0
T2	72245	4717	0	0
T3	11961	0	0	0
T4	447757	0	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	13426	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T14	0	3928	0	0
T26	84072	0	0	0
T63	0	38031	0	0
T104	0	25768	0	0
T205	0	6226	0	0
T208	0	3099	0	0
T209	0	14814	0	0
T210	0	21101	0	0
T211	0	1809	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	16714523	0	0
T2	72245	64886	0	0
T3	11961	0	0	0
T4	447757	0	0	0
T5	43899	0	0	0
T8	14358	0	0	0
T9	14944	0	0	0
T10	414343	172074	0	0
T11	5211	0	0	0
T12	79060	0	0	0
T14	0	110913	0	0
T26	84072	0	0	0
T63	0	120359	0	0
T96	0	88039	0	0
T98	0	34419	0	0
T101	0	3983	0	0
T104	0	147883	0	0
T108	0	2921	0	0
T212	0	2927	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512931934	512068706	0	0
T1	11900	11640	0	0
T2	72245	71111	0	0
T3	11961	11687	0	0
T4	447757	447742	0	0
T5	43899	43095	0	0
T8	14358	14100	0	0
T9	14944	14674	0	0
T10	414343	407956	0	0
T11	5211	5154	0	0
T12	79060	78403	0	0