Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1451020
Category 01451020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1451020
Severity 01451020

Summary for Assertions
NUMBERPERCENT
Total Number1451100.00
Uncovered553.79
Success139696.21
Failure00.00
Incomplete110.76
Without Attempts50.34

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_otp_ctrl_dai.ScrmblMtxReqKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.ScrmblSelKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.ScrmblValidKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.gen_part_sel[0].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[10].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[1].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[2].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[3].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[4].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[5].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[6].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[7].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[8].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.gen_part_sel[9].PartEndMax_A 001158115800
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckHotOne_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.CheckNGreaterZero_A 001158115800
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.GrantKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.IdxKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.Priority_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ReqImpliesValid_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.u_part_sel_idx.ValidKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_dai.u_state_regs.AssertConnected_A 001158115800
tb.dut.u_otp_ctrl_dai.u_state_regs_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.EdnReqKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.EntropyWidthDividesDigestBlockWidth_A 001158115800
tb.dut.u_otp_ctrl_kdi.FlashOtpKeyRspKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.FsmErrKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.KeyNonceSize0_A 001158115800
tb.dut.u_otp_ctrl_kdi.KeyNonceSize1_A 001158115800
tb.dut.u_otp_ctrl_kdi.KeyNonceSize2_A 001158115800
tb.dut.u_otp_ctrl_kdi.KeyNonceSize3_A 001158115800
tb.dut.u_otp_ctrl_kdi.KeyNonceSize4_A 001158115800
tb.dut.u_otp_ctrl_kdi.KeyNonceSize5_A 001158115800
tb.dut.u_otp_ctrl_kdi.KeyNonceSize6_A 001158115800
tb.dut.u_otp_ctrl_kdi.NonceWidth_A 001158115800
tb.dut.u_otp_ctrl_kdi.OtbnOtpKeyRspKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.ScrmblCmdKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.ScrmblDataKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.ScrmblModeKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.ScrmblMtxReqKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.ScrmblSelKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.ScrmblValidKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.SramOtpKeyRspKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckHotOne_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.u_req_arb.CheckNGreaterZero_A 001158115800
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesReady_A 005068092034768800
tb.dut.u_otp_ctrl_kdi.u_req_arb.GntImpliesValid_A 005068092034768800
tb.dut.u_otp_ctrl_kdi.u_req_arb.GrantKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.u_req_arb.IdxKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.u_req_arb.IndexIsCorrect_A 005068092034768800
tb.dut.u_otp_ctrl_kdi.u_req_arb.LockArbDecision_A 005068092037430615100
tb.dut.u_otp_ctrl_kdi.u_req_arb.NoReadyValidNoGrant_A 0050680920343153247700
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReadyAndValidImplyGrant_A 005068092034768800
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqAndReadyImplyGrant_A 005068092034768800
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqImpliesValid_A 005068092037435630300
tb.dut.u_otp_ctrl_kdi.u_req_arb.ReqStaysHighUntilGranted0_M 005068092037430615100
tb.dut.u_otp_ctrl_kdi.u_req_arb.ValidKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_kdi.u_req_arb.gen_data_port_assertion.DataFlow_A 005068092034768800
tb.dut.u_otp_ctrl_kdi.u_state_regs.AssertConnected_A 001158115800
tb.dut.u_otp_ctrl_kdi.u_state_regs_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.ErrorKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.LcAckKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.LcErrKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.LcValueMustBeWiderThanNativeOtpWidth_A 001158115800
tb.dut.u_otp_ctrl_lci.LciIdleKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.OtpAddrKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.OtpCmdKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.OtpReqKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.OtpSizeKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.OtpWdataKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lci.u_state_regs.AssertConnected_A 001158115800
tb.dut.u_otp_ctrl_lci.u_state_regs_A 0050680920350588878000
tb.dut.u_otp_ctrl_lfsr_timer.ChkPendingKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lfsr_timer.ChkTimeoutKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lfsr_timer.CnstyChkReqKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lfsr_timer.EdnIsWideEnough_A 001158115800
tb.dut.u_otp_ctrl_lfsr_timer.EdnReqKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lfsr_timer.IntegChkReqKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A 001158115800
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A 001158115800
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A 0050680920350588878000
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A 0050680920326700100
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A 0050680920316418200
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A 0050680920328875600
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A 0050680920350588878000
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A 001158115800
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A 0050680920350588878000
tb.dut.u_otp_rsp_fifo.DataKnown_A 005068092031843846100
tb.dut.u_otp_rsp_fifo.DepthKnown_A 0050680920350588878000
tb.dut.u_otp_rsp_fifo.RvalidKnown_A 0050680920350588878000
tb.dut.u_otp_rsp_fifo.WreadyKnown_A 0050680920350588878000
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 005068092031843846100
tb.dut.u_part_sel_idx.CheckHotOne_A 0050680920350588878000
tb.dut.u_part_sel_idx.CheckNGreaterZero_A 001158115800
tb.dut.u_part_sel_idx.GrantKnown_A 0050680920350588878000
tb.dut.u_part_sel_idx.IdxKnown_A 0050680920350588878000
tb.dut.u_part_sel_idx.Priority_A 0050680920350588878000
tb.dut.u_part_sel_idx.ReqImpliesValid_A 0050680920350588878000
tb.dut.u_part_sel_idx.ValidKnown_A 0050680920350588878000
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A 0050680920328395337900
tb.dut.u_prim_edn_req.DataOutputValid_A 0050680920329965200
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 0050680920359986400
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 0050680920359975600
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 00145577950860014400
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 0050680920329927300
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A 001158115800
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A 0050680920350588878000
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001158115800
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A 0050680920350588878000
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A 001158115800
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A 0050680920350588878000
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A 001158115800
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A 0050680920350588878000
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001158115800
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A 0050680920350588878000
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A 001158115800
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A 0050680920350588878000
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_reg_core.en2addrHit 005096268181024450100
tb.dut.u_reg_core.reAfterRv 005096268181024449900
tb.dut.u_reg_core.rePulse 00509626818824407100
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001333133300
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001333133300
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001333133300
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001333133300
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001333133300
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001333133300
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001333133300
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001333133300
tb.dut.u_reg_core.u_socket.NotOverflowed_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 005096268186811449900
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 005096268186868932900
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 005096268182890632100
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 005096268182508156600
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 005096268182873299100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 005096268184360776300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0050962681850865750500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.maxN 001333133300
tb.dut.u_reg_core.wePulse 00509626818200042800
tb.dut.u_scrmbl_mtx.CheckHotOne_A 0050680920350588878000
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A 001158115800
tb.dut.u_scrmbl_mtx.GrantKnown_A 0050680920350588878000
tb.dut.u_scrmbl_mtx.IdxKnown_A 0050680920350588878000
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A 0050680920345812950400
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A 005068092034775927600
tb.dut.u_scrmbl_mtx.ValidKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A 001158115800
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A 001158115800
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A 001158115800
tb.dut.u_tlul_adapter_sram.TlOutKnownIfFifoKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.TlOutValidKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.WeOutKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite 001158115800
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty 0050680920310166800
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull 0050680920310166800
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A 001158115800
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A 005068092032556286100
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 005068092032556286100
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A 001158115800
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck 001158115800
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A 0050680920326107400
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0050680920326107400
tb.dut.u_tlul_adapter_sram.u_sram_byte.SramReadbackAndIntg 001158115800
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A 0050680920359926200
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A 0050680920350588878000
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0050680920359926200
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001158115800
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A 0050680920350588878000
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0050680920350588878000
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A 001158115800
tb.dut.u_tlul_lc_gate.u_state_regs_A 0050680920350588878000
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001158115800
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001158115800

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_edn_arb.RoundRobin_A 00506809203001158
tb.dut.u_otp_arb.RoundRobin_A 00506809203001158
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A 00506809203001158
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 00506809203001158
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 0050680920350584563503474
tb.dut.u_scrmbl_mtx.RoundRobin_A 00506809203001158

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A 000000

Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 005096277127207200
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 005096277121381380
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 005096277121401400
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0050962771288880
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0050962771218180
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0050962771273730
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0050962771283830
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00509627712414841480
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 00509627712736973690
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 00509627712360111636011161226
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 005096277123053050
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0050962771250500
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0050962771255550
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0050962771239390
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00509627712550
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0050962771230300
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00509627712440
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00509627712125212520
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 00509627712260726070
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 00509627712620486204858

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 005096277127207200
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 005096277121381380
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 005096277121401400
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0050962771288880
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0050962771218180
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0050962771273730
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0050962771283830
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00509627712414841480
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 00509627712736973690
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 00509627712360111636011161226
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 005096277123053050
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0050962771250500
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0050962771255550
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0050962771239390
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00509627712550
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0050962771230300
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00509627712440
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00509627712125212520
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 00509627712260726070
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 00509627712620486204858