Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

27136542

1

T1

105

T2

784

T3

1637

full_word

8989595

1

T1

36

T2

245

T3

688

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36125867	1			T1	141		T2	1029		T3	2325
auto[TlIntgErrCmd]	80	1			T275	3		T276	11		T287	5
auto[TlIntgErrData]	95	1			T274	5		T275	2		T276	6
auto[TlIntgErrBoth]	95	1			T274	5		T275	5		T276	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10912536

1

T1

1

T2

761

T3

2108

auto[1]

25213601

1

T1

140

T2

268

T3

217

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6915064	1			T2	643		T3	1500		T4	43229
auto[TlIntgErrNone]	partial	auto[1]	20221236	1			T1	105		T2	141		T3	137
auto[TlIntgErrNone]	full_word	auto[0]	3997356	1			T1	1		T2	118		T3	608
auto[TlIntgErrNone]	full_word	auto[1]	4992211	1			T1	35		T2	127		T3	80
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T275	1		T276	3		T287	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T275	2		T276	8		T287	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T362	1		T363	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T288	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1			T274	3		T275	1		T276	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T274	2		T275	1		T276	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T276	1		T287	1		T360	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T287	1		T364	1		T361	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T274	1		T275	1		T276	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T274	4		T275	2		T276	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T275	1		T288	1		T364	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T275	1		T287	1		T361	1