Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	509626818	8578893	0	0
check_regwen_rd_A	509626818	3793	0	0
check_timeout_rd_A	509626818	2928	0	0
check_trigger_regwen_rd_A	509626818	3975	0	0
consistency_check_period_rd_A	509626818	4028	0	0
creator_sw_cfg_read_lock_rd_A	509626818	3057	0	0
direct_access_address_rd_A	509626818	2842	0	0
direct_access_wdata_0_rd_A	509626818	1713	0	0
direct_access_wdata_1_rd_A	509626818	2049	0	0
integrity_check_period_rd_A	509626818	3604	0	0
intr_enable_rd_A	509626818	4687	0	0
owner_sw_cfg_read_lock_rd_A	509626818	2884	0	0
rot_creator_auth_codesign_read_lock_rd_A	509626818	3467	0	0
rot_creator_auth_state_read_lock_rd_A	509626818	2631	0	0
vendor_test_read_lock_rd_A	509626818	2822	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	8578893	0	0
T4	374436	84902	0	0
T5	23884	0	0	0
T6	131424	17835	0	0
T7	0	15281	0	0
T8	10345	0	0	0
T9	10638	0	0	0
T10	184952	0	0	0
T11	53223	0	0	0
T12	10914	0	0	0
T13	0	22342	0	0
T14	0	92692	0	0
T15	86814	0	0	0
T16	0	98435	0	0
T63	12003	0	0	0
T64	0	28923	0	0
T187	0	18424	0	0
T223	0	123096	0	0
T235	0	28670	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	3793	0	0
T14	661284	60	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	64	0	0
T247	48307	0	0	0
T268	0	124	0	0
T290	0	102	0	0
T291	0	158	0	0
T337	0	141	0	0
T338	0	189	0	0
T339	0	47	0	0
T340	0	31	0	0
T341	0	53	0	0
T342	7236	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	2928	0	0
T14	661284	93	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	60	0	0
T247	48307	0	0	0
T268	0	136	0	0
T290	0	74	0	0
T291	0	107	0	0
T337	0	96	0	0
T338	0	291	0	0
T339	0	39	0	0
T340	0	21	0	0
T341	0	44	0	0
T342	7236	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	3975	0	0
T14	661284	84	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	62	0	0
T247	48307	0	0	0
T268	0	120	0	0
T290	0	27	0	0
T291	0	135	0	0
T337	0	65	0	0
T338	0	179	0	0
T339	0	49	0	0
T340	0	32	0	0
T341	0	84	0	0
T342	7236	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	4028	0	0
T14	661284	66	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	139	0	0
T247	48307	0	0	0
T268	0	114	0	0
T290	0	48	0	0
T291	0	85	0	0
T337	0	141	0	0
T338	0	203	0	0
T339	0	43	0	0
T340	0	29	0	0
T341	0	91	0	0
T342	7236	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	3057	0	0
T14	661284	67	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	102	0	0
T247	48307	0	0	0
T268	0	128	0	0
T290	0	92	0	0
T291	0	126	0	0
T337	0	109	0	0
T338	0	195	0	0
T339	0	49	0	0
T340	0	47	0	0
T341	0	99	0	0
T342	7236	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	2842	0	0
T14	661284	66	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	83	0	0
T247	48307	0	0	0
T268	0	111	0	0
T290	0	60	0	0
T291	0	86	0	0
T337	0	71	0	0
T338	0	222	0	0
T339	0	51	0	0
T340	0	26	0	0
T341	0	105	0	0
T342	7236	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	1713	0	0
T14	661284	58	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	63	0	0
T247	48307	0	0	0
T268	0	88	0	0
T290	0	69	0	0
T291	0	78	0	0
T337	0	21	0	0
T338	0	126	0	0
T339	0	37	0	0
T340	0	6	0	0
T341	0	71	0	0
T342	7236	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	2049	0	0
T14	661284	30	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	67	0	0
T247	48307	0	0	0
T268	0	46	0	0
T290	0	58	0	0
T291	0	86	0	0
T337	0	48	0	0
T338	0	202	0	0
T339	0	29	0	0
T340	0	12	0	0
T341	0	50	0	0
T342	7236	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	3604	0	0
T14	661284	82	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	63	0	0
T247	48307	0	0	0
T268	0	146	0	0
T290	0	58	0	0
T291	0	122	0	0
T337	0	45	0	0
T338	0	158	0	0
T339	0	61	0	0
T340	0	23	0	0
T341	0	33	0	0
T342	7236	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	4687	0	0
T14	661284	58	0	0
T66	0	20	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T121	0	10	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	67	0	0
T247	48307	0	0	0
T261	0	11	0	0
T268	0	129	0	0
T290	0	79	0	0
T337	0	97	0	0
T338	0	246	0	0
T339	0	26	0	0
T342	7236	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	2884	0	0
T14	661284	70	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	76	0	0
T247	48307	0	0	0
T268	0	130	0	0
T290	0	63	0	0
T291	0	150	0	0
T337	0	95	0	0
T338	0	175	0	0
T339	0	48	0	0
T340	0	5	0	0
T341	0	103	0	0
T342	7236	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	3467	0	0
T14	661284	96	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	175	0	0
T247	48307	0	0	0
T268	0	143	0	0
T290	0	76	0	0
T291	0	176	0	0
T337	0	70	0	0
T338	0	279	0	0
T339	0	55	0	0
T340	0	12	0	0
T341	0	112	0	0
T342	7236	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	2631	0	0
T14	661284	75	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	47	0	0
T247	48307	0	0	0
T268	0	104	0	0
T290	0	78	0	0
T291	0	119	0	0
T337	0	78	0	0
T338	0	196	0	0
T339	0	63	0	0
T340	0	16	0	0
T341	0	86	0	0
T342	7236	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509626818	2822	0	0
T14	661284	81	0	0
T92	178284	0	0	0
T93	247745	0	0	0
T96	21842	0	0	0
T139	16652	0	0	0
T187	187411	0	0	0
T219	32116	0	0	0
T220	27213	0	0	0
T223	0	93	0	0
T247	48307	0	0	0
T268	0	114	0	0
T290	0	112	0	0
T291	0	106	0	0
T337	0	88	0	0
T338	0	178	0	0
T339	0	69	0	0
T340	0	32	0	0
T341	0	48	0	0
T342	7236	0	0	0