Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T130,T23,T24

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T69,T58,T48

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T131
1	Covered	T131

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T2,T4,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T11
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T4,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T4,T8
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T12,T139,T140
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T9,T97,T175
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T10,T11
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T142,T143,T189
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T66,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T10,T11
CheckFailError	317	Covered	T131
FsmStateError	289	Covered	T2,T4,T8
MacroEccCorrError	221	Covered	T69,T58,T48
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T10,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T131
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T4,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T130,T142,T136
MacroEccCorrError->NoError	235	Covered	T69,T58,T48
NoError->AccessError	256	Covered	T4,T10,T11
NoError->CheckFailError	317	Covered	T131
NoError->FsmStateError	289	Covered	T2,T4,T8
NoError->MacroEccCorrError	221	Covered	T69,T58,T48

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T130,T23,T24
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T97,T175,T133
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T16,T121,T122
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T10,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T69,T58,T48
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T142,T143,T189
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T6,T63
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T6,T63
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T4,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T131
1	0	Covered	T131
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	506809203	505888780	0	0
DigestKnown_A	506809203	505888780	0	0
DigestOffsetMustBeRepresentable_A	1158	1158	0	0
EccErrorState_A	506809203	3900	0	0
ErrorKnown_A	506809203	505888780	0	0
FsmStateKnown_A	506809203	505888780	0	0
InitDoneKnown_A	506809203	505888780	0	0
InitReadLocksPartition_A	506809203	114533599	0	0
InitWriteLocksPartition_A	506809203	114533599	0	0
OffsetMustBeBlockAligned_A	1158	1158	0	0
OtpAddrKnown_A	506809203	505888780	0	0
OtpCmdKnown_A	506809203	505888780	0	0
OtpErrorState_A	506809203	51	0	0
OtpReqKnown_A	506809203	505888780	0	0
OtpSizeKnown_A	506809203	505888780	0	0
OtpWdataKnown_A	506809203	505888780	0	0
ReadLockPropagation_A	506809203	225193553	0	0
SizeMustBeBlockAligned_A	1158	1158	0	0
TlulGntKnown_A	506809203	505888780	0	0
TlulRdataKnown_A	506809203	505888780	0	0
TlulReadOnReadLock_A	506809203	9535	0	0
TlulRerrorKnown_A	506809203	505888780	0	0
TlulRvalidKnown_A	506809203	505888780	0	0
WriteLockPropagation_A	506809203	3018913	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	506809203	30742021	0	0
u_state_regs_A	506809203	505888780	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	3900	0	0
T131	14715	3900	0	0
T190	57459	0	0	0
T191	11076	0	0	0
T192	22056	0	0	0
T193	133467	0	0	0
T194	17309	0	0	0
T195	24609	0	0	0
T196	57045	0	0	0
T197	16627	0	0	0
T198	10177	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	114533599	0	0
T1	18167	907	0	0
T2	11437	4275	0	0
T3	45277	1159	0	0
T4	374436	960856	0	0
T5	23884	629	0	0
T8	10345	5016	0	0
T9	10638	4288	0	0
T10	184952	1499	0	0
T11	53223	2087	0	0
T12	10914	4289	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	114533599	0	0
T1	18167	907	0	0
T2	11437	4275	0	0
T3	45277	1159	0	0
T4	374436	960856	0	0
T5	23884	629	0	0
T8	10345	5016	0	0
T9	10638	4288	0	0
T10	184952	1499	0	0
T11	53223	2087	0	0
T12	10914	4289	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	51	0	0
T65	9652	0	0	0
T79	15569	0	0	0
T87	47053	0	0	0
T97	10742	1	0	0
T98	16707	0	0	0
T99	13620	0	0	0
T100	23471	0	0	0
T101	55451	0	0	0
T129	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T142	0	1	0	0
T144	30743	0	0	0
T175	12504	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	225193553	0	0
T3	45277	4883	0	0
T4	374436	195109	0	0
T5	23884	0	0	0
T6	131424	482785	0	0
T8	10345	0	0	0
T9	10638	0	0	0
T10	184952	64419	0	0
T11	53223	10167	0	0
T12	10914	0	0	0
T15	86814	23080	0	0
T87	0	7070	0	0
T88	0	11015	0	0
T100	0	8078	0	0
T144	0	23475	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	9535	0	0
T4	374436	70	0	0
T5	23884	0	0	0
T6	131424	23	0	0
T8	10345	0	0	0
T9	10638	0	0	0
T10	184952	11	0	0
T11	53223	3	0	0
T12	10914	0	0	0
T15	86814	3	0	0
T63	12003	1	0	0
T87	0	2	0	0
T88	0	23	0	0
T99	0	2	0	0
T144	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	3018913	0	0
T6	131424	0	0	0
T10	184952	35001	0	0
T11	53223	2070	0	0
T12	10914	0	0	0
T15	86814	0	0	0
T58	0	1253	0	0
T63	12003	0	0	0
T87	47053	0	0	0
T88	0	6313	0	0
T89	0	26482	0	0
T90	0	3718	0	0
T91	0	21985	0	0
T92	0	26000	0	0
T93	0	17716	0	0
T97	10742	0	0	0
T98	16707	0	0	0
T99	13620	0	0	0
T117	0	4641	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	30742021	0	0
T3	45277	4801	0	0
T4	374436	0	0	0
T5	23884	0	0	0
T6	131424	0	0	0
T8	10345	0	0	0
T9	10638	0	0	0
T10	184952	162699	0	0
T11	53223	43377	0	0
T12	10914	0	0	0
T15	86814	61501	0	0
T87	0	17261	0	0
T88	0	55384	0	0
T89	0	78752	0	0
T90	0	39372	0	0
T175	0	3629	0	0
T178	0	10109	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T105,T32

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T48,T138,T136

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T137,T132
1	Covered	T74,T137,T132

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T2,T4,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T10
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T87,T65

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T87,T65

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T4,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T4,T8
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T9,T12,T139
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T97,T65,T175
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T10
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T141,T136,T171
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T66,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T4,T10
CheckFailError	317	Covered	T74,T137,T132
FsmStateError	289	Covered	T2,T4,T8
MacroEccCorrError	221	Covered	T48,T39,T138
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T6,T144
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T4,T10
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T74,T137,T132
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T4,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T39,T136,T143
MacroEccCorrError->NoError	235	Covered	T48,T138,T83
NoError->AccessError	256	Covered	T3,T4,T10
NoError->CheckFailError	317	Covered	T74,T137,T132
NoError->FsmStateError	289	Covered	T2,T4,T8
NoError->MacroEccCorrError	221	Covered	T48,T39,T138

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T87,T65
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T39,T105,T32
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T65,T130,T203
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T88,T121,T122
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T48,T138,T136
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T141,T136,T171
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T6,T63
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T6,T63
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T4,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T137,T132
1	0	Covered	T74,T137,T132
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	506809203	505888780	0	0
DigestKnown_A	506809203	505888780	0	0
DigestOffsetMustBeRepresentable_A	1158	1158	0	0
EccErrorState_A	506809203	9226	0	0
ErrorKnown_A	506809203	505888780	0	0
FsmStateKnown_A	506809203	505888780	0	0
InitDoneKnown_A	506809203	505888780	0	0
InitReadLocksPartition_A	506809203	114725628	0	0
InitWriteLocksPartition_A	506809203	114725628	0	0
OffsetMustBeBlockAligned_A	1158	1158	0	0
OtpAddrKnown_A	506809203	505888780	0	0
OtpCmdKnown_A	506809203	505888780	0	0
OtpErrorState_A	506809203	43	0	0
OtpReqKnown_A	506809203	505888780	0	0
OtpSizeKnown_A	506809203	505888780	0	0
OtpWdataKnown_A	506809203	505888780	0	0
ReadLockPropagation_A	506809203	228553300	0	0
SizeMustBeBlockAligned_A	1158	1158	0	0
TlulGntKnown_A	506809203	505888780	0	0
TlulRdataKnown_A	506809203	505888780	0	0
TlulReadOnReadLock_A	506809203	9157	0	0
TlulRerrorKnown_A	506809203	505888780	0	0
TlulRvalidKnown_A	506809203	505888780	0	0
WriteLockPropagation_A	506809203	927580	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	506809203	11446195	0	0
u_state_regs_A	506809203	505888780	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	9226	0	0
T29	12697	0	0	0
T74	15070	3691	0	0
T104	14532	0	0	0
T132	0	3226	0	0
T137	0	2309	0	0
T204	17702	0	0	0
T205	10609	0	0	0
T206	14851	0	0	0
T207	11780	0	0	0
T208	35128	0	0	0
T209	170406	0	0	0
T210	3863	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	114725628	0	0
T1	18167	924	0	0
T2	11437	4326	0	0
T3	45277	1329	0	0
T4	374436	961043	0	0
T5	23884	731	0	0
T8	10345	5050	0	0
T9	10638	4305	0	0
T10	184952	1720	0	0
T11	53223	2314	0	0
T12	10914	4323	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	114725628	0	0
T1	18167	924	0	0
T2	11437	4326	0	0
T3	45277	1329	0	0
T4	374436	961043	0	0
T5	23884	731	0	0
T8	10345	5050	0	0
T9	10638	4305	0	0
T10	184952	1720	0	0
T11	53223	2314	0	0
T12	10914	4323	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	43	0	0
T43	12406	0	0	0
T65	9652	1	0	0
T79	15569	0	0	0
T88	77671	0	0	0
T89	102684	0	0	0
T90	51085	0	0	0
T100	23471	0	0	0
T101	55451	0	0	0
T130	0	1	0	0
T136	0	1	0	0
T141	0	1	0	0
T171	0	1	0	0
T175	12504	0	0	0
T178	18322	0	0	0
T203	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	228553300	0	0
T3	45277	6094	0	0
T4	374436	195108	0	0
T5	23884	0	0	0
T6	131424	675745	0	0
T8	10345	0	0	0
T9	10638	0	0	0
T10	184952	67042	0	0
T11	53223	5179	0	0
T12	10914	0	0	0
T15	86814	25255	0	0
T87	0	6329	0	0
T88	0	7761	0	0
T100	0	8606	0	0
T144	0	23473	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	9157	0	0
T3	45277	1	0	0
T4	374436	66	0	0
T5	23884	0	0	0
T6	131424	19	0	0
T8	10345	0	0	0
T9	10638	0	0	0
T10	184952	11	0	0
T11	53223	0	0	0
T12	10914	0	0	0
T15	86814	4	0	0
T63	0	1	0	0
T87	0	3	0	0
T98	0	6	0	0
T99	0	1	0	0
T144	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	927580	0	0
T6	131424	0	0	0
T11	53223	1778	0	0
T12	10914	0	0	0
T15	86814	0	0	0
T63	12003	0	0	0
T87	47053	0	0	0
T90	0	2639	0	0
T92	0	20852	0	0
T94	0	2366	0	0
T97	10742	0	0	0
T98	16707	0	0	0
T99	13620	0	0	0
T121	0	24348	0	0
T122	0	9761	0	0
T144	30743	0	0	0
T215	0	15149	0	0
T216	0	10801	0	0
T217	0	19639	0	0
T218	0	46420	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	11446195	0	0
T6	131424	0	0	0
T11	53223	43167	0	0
T12	10914	0	0	0
T15	86814	0	0	0
T63	12003	0	0	0
T65	0	3580	0	0
T87	47053	27691	0	0
T90	0	39185	0	0
T92	0	159233	0	0
T94	0	34879	0	0
T97	10742	0	0	0
T98	16707	0	0	0
T99	13620	0	0	0
T117	0	48183	0	0
T144	30743	0	0	0
T182	0	2900	0	0
T219	0	2637	0	0
T220	0	10810	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506809203	505888780	0	0
T1	18167	18112	0	0
T2	11437	11183	0	0
T3	45277	44313	0	0
T4	374436	374423	0	0
T5	23884	23411	0	0
T8	10345	10058	0	0
T9	10638	10356	0	0
T10	184952	183893	0	0
T11	53223	52170	0	0
T12	10914	10691	0	0