SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
83.33 | 63.89 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
buf_err_code_cg_wrap[OtpSecret0ErrIdx] | 0.00 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx] | 66.67 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx] | 66.67 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 6 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
66.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 2 | 4 | 66.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 2 | 4 | 66.67 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
66.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 2 | 4 | 66.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 2 | 4 | 66.67 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 6 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
fsm_err | 0 | 1 | 1 | |
check_fail | 0 | 1 | 1 | |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 | |
no_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 2 | 4 | 66.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 118117 | 1 | T1 | 17 | T3 | 1 | T4 | 754 | ||||
check_fail | 5 | 1 | T54 | 1 | T55 | 1 | T56 | 1 | ||||
ecc_uncorr_err | 400 | 1 | T72 | 34 | T73 | 73 | T37 | 1 | ||||
no_err | 153243 | 1 | T1 | 29 | T2 | 44 | T4 | 1322 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 2 | 4 | 66.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
check_fail | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 118421 | 1 | T1 | 17 | T4 | 754 | T9 | 21 | ||||
ecc_uncorr_err | 91 | 1 | T50 | 1 | T74 | 11 | T44 | 1 | ||||
ecc_corr_err | 178 | 1 | T33 | 79 | T34 | 50 | T35 | 13 | ||||
no_err | 152976 | 1 | T1 | 29 | T2 | 44 | T4 | 1322 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 118419 | 1 | T1 | 11 | T3 | 1 | T4 | 754 | ||||
check_fail | 12 | 1 | T27 | 1 | T28 | 1 | T29 | 1 | ||||
ecc_uncorr_err | 91 | 1 | T1 | 6 | T59 | 1 | T60 | 1 | ||||
ecc_corr_err | 60 | 1 | T25 | 26 | T26 | 34 | - | - | ||||
no_err | 153453 | 1 | T1 | 29 | T2 | 44 | T4 | 1322 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 118338 | 1 | T1 | 17 | T4 | 754 | T9 | 21 | ||||
check_fail | 27 | 1 | T40 | 1 | T41 | 1 | T42 | 1 | ||||
ecc_uncorr_err | 143 | 1 | T75 | 51 | T22 | 1 | T106 | 1 | ||||
ecc_corr_err | 78 | 1 | T38 | 52 | T39 | 26 | - | - | ||||
no_err | 153337 | 1 | T1 | 29 | T2 | 44 | T4 | 1322 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 118167 | 1 | T1 | 17 | T3 | 1 | T4 | 754 | ||||
check_fail | 15 | 1 | T47 | 1 | T48 | 1 | T49 | 1 | ||||
ecc_uncorr_err | 323 | 1 | T57 | 1 | T74 | 12 | T113 | 1 | ||||
ecc_corr_err | 126 | 1 | T45 | 45 | T25 | 27 | T46 | 28 | ||||
no_err | 153211 | 1 | T1 | 29 | T2 | 44 | T4 | 1322 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |