Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7120589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7195589

1

T1

530

T2

413

T3

151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8245579	1			T1	1647		T2	914		T3	277
values[0x0]	2310810	1			T1	103		T2	71		T3	94
values[0x1]	3759789	1			T1	104		T2	77		T3	81

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4610500	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9705678

1

T1

902

T2

561

T3

227

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	59460	1			T2	5		T8	1		T9	6
valid_sources[0x01]	131152	1			T1	15		T2	6		T8	4
valid_sources[0x02]	50045	1			T97	7		T7	367		T188	15
valid_sources[0x03]	50097	1			T1	15		T2	5		T9	5
valid_sources[0x04]	58351	1			T1	9		T2	5		T8	1
valid_sources[0x05]	55668	1			T1	11		T8	2		T9	9
valid_sources[0x06]	50848	1			T1	23		T2	7		T8	6
valid_sources[0x07]	47617	1			T2	10		T8	1		T97	3
valid_sources[0x08]	57620	1			T1	3		T2	5		T8	1
valid_sources[0x09]	49089	1			T1	11		T2	12		T8	1
valid_sources[0x0a]	49276	1			T1	10		T2	3		T8	1
valid_sources[0x0b]	47697	1			T2	3		T8	2		T97	2
valid_sources[0x0c]	46802	1			T1	11		T2	6		T8	1
valid_sources[0x0d]	47164	1			T1	17		T2	3		T8	3
valid_sources[0x0e]	59673	1			T2	1		T9	21		T97	3
valid_sources[0x0f]	58771	1			T1	6		T2	12		T8	2
valid_sources[0x10]	48426	1			T1	8		T2	4		T8	1
valid_sources[0x11]	48093	1			T2	5		T8	3		T58	1
valid_sources[0x12]	58073	1			T1	6		T2	2		T8	1
valid_sources[0x13]	56539	1			T1	5		T2	12		T8	1
valid_sources[0x14]	48840	1			T1	1		T2	7		T8	1
valid_sources[0x15]	51257	1			T2	1		T9	13		T97	5
valid_sources[0x16]	51244	1			T1	11		T2	3		T8	1
valid_sources[0x17]	57362	1			T1	3		T8	2		T97	5
valid_sources[0x18]	60979	1			T1	36		T2	1		T8	3
valid_sources[0x19]	150567	1			T2	9		T8	5		T9	18
valid_sources[0x1a]	53262	1			T1	4		T2	8		T8	2
valid_sources[0x1b]	54239	1			T1	21		T2	3		T8	1
valid_sources[0x1c]	53723	1			T1	2		T8	2		T97	6
valid_sources[0x1d]	49345	1			T2	7		T8	2		T9	8
valid_sources[0x1e]	49123	1			T2	9		T8	2		T9	15
valid_sources[0x1f]	66301	1			T1	7		T8	2		T9	12
valid_sources[0x20]	48073	1			T1	11		T8	4		T9	4
valid_sources[0x21]	52156	1			T1	3		T8	6		T97	3
valid_sources[0x22]	52205	1			T1	6		T2	9		T8	2
valid_sources[0x23]	52958	1			T1	13		T2	6		T9	5
valid_sources[0x24]	55382	1			T1	1		T2	1		T8	5
valid_sources[0x25]	50015	1			T1	1		T2	2		T8	2
valid_sources[0x26]	50041	1			T1	7		T2	5		T8	1
valid_sources[0x27]	51864	1			T1	15		T2	8		T8	3
valid_sources[0x28]	52943	1			T1	6		T2	6		T8	4
valid_sources[0x29]	54930	1			T1	1		T2	2		T8	3
valid_sources[0x2a]	55945	1			T1	3		T2	1		T8	1
valid_sources[0x2b]	52207	1			T2	1		T8	3		T9	1
valid_sources[0x2c]	59881	1			T1	7		T2	6		T8	1
valid_sources[0x2d]	50312	1			T1	15		T2	4		T8	2
valid_sources[0x2e]	53830	1			T1	3		T8	2		T9	16
valid_sources[0x2f]	49903	1			T1	2		T2	10		T8	1
valid_sources[0x30]	53885	1			T1	3		T2	14		T8	5
valid_sources[0x31]	118690	1			T1	1		T9	18		T97	6
valid_sources[0x32]	51454	1			T1	2		T3	452		T8	4
valid_sources[0x33]	54163	1			T1	7		T2	3		T8	4
valid_sources[0x34]	50737	1			T2	6		T8	1		T7	365
valid_sources[0x35]	54726	1			T2	1		T8	4		T97	1
valid_sources[0x36]	48349	1			T1	23		T2	5		T8	3
valid_sources[0x37]	57495	1			T1	4		T2	2		T8	3
valid_sources[0x38]	48005	1			T1	8		T2	7		T9	1
valid_sources[0x39]	53293	1			T1	3		T9	31		T97	4
valid_sources[0x3a]	62560	1			T1	22		T2	2		T8	1
valid_sources[0x3b]	55793	1			T1	17		T2	6		T8	3
valid_sources[0x3c]	49237	1			T2	3		T8	3		T9	3
valid_sources[0x3d]	51244	1			T1	10		T2	4		T8	1
valid_sources[0x3e]	49467	1			T1	14		T8	2		T9	7
valid_sources[0x3f]	49296	1			T1	13		T2	11		T9	13
valid_sources[0x40]	68156	1			T2	1		T8	1		T9	4
valid_sources[0x41]	109750	1			T1	6		T2	6		T4	52473
valid_sources[0x42]	60067	1			T1	2		T2	2		T8	3
valid_sources[0x43]	52225	1			T1	3		T2	14		T8	2
valid_sources[0x44]	57384	1			T1	12		T2	3		T8	2
valid_sources[0x45]	54039	1			T1	4		T2	7		T8	1
valid_sources[0x46]	53957	1			T1	5		T2	3		T8	1
valid_sources[0x47]	49937	1			T1	14		T2	4		T8	3
valid_sources[0x48]	51497	1			T8	2		T9	3		T97	3
valid_sources[0x49]	49873	1			T1	23		T8	4		T9	17
valid_sources[0x4a]	56019	1			T1	9		T8	1		T9	3
valid_sources[0x4b]	60354	1			T1	4		T2	4		T9	7
valid_sources[0x4c]	50212	1			T1	8		T2	2		T97	3
valid_sources[0x4d]	67581	1			T1	17		T8	1		T97	1
valid_sources[0x4e]	53550	1			T1	7		T2	13		T8	3
valid_sources[0x4f]	51785	1			T1	17		T2	8		T8	1
valid_sources[0x50]	69132	1			T1	5		T2	2		T8	2
valid_sources[0x51]	55846	1			T1	8		T2	8		T8	4
valid_sources[0x52]	50904	1			T1	11		T2	3		T8	1
valid_sources[0x53]	51566	1			T1	15		T8	4		T9	3
valid_sources[0x54]	50492	1			T1	14		T8	1		T9	4
valid_sources[0x55]	49837	1			T1	3		T2	5		T8	2
valid_sources[0x56]	48519	1			T1	2		T2	13		T8	4
valid_sources[0x57]	72681	1			T8	2		T9	6		T97	2
valid_sources[0x58]	53547	1			T1	2		T2	1		T8	4
valid_sources[0x59]	58191	1			T1	5		T9	5		T97	4
valid_sources[0x5a]	54659	1			T1	6		T8	2		T9	2
valid_sources[0x5b]	51623	1			T2	13		T8	4		T97	2
valid_sources[0x5c]	52421	1			T1	3		T2	6		T8	1
valid_sources[0x5d]	48683	1			T2	4		T8	2		T9	2
valid_sources[0x5e]	68678	1			T1	1		T2	5		T8	4
valid_sources[0x5f]	56462	1			T8	2		T9	8		T97	5
valid_sources[0x60]	58563	1			T1	8		T2	14		T8	1
valid_sources[0x61]	53781	1			T1	9		T2	7		T9	31
valid_sources[0x62]	51043	1			T1	7		T2	8		T8	2
valid_sources[0x63]	52262	1			T2	9		T8	2		T9	3
valid_sources[0x64]	52398	1			T1	10		T2	5		T8	1
valid_sources[0x65]	56523	1			T1	15		T8	2		T9	7
valid_sources[0x66]	50914	1			T1	4		T2	5		T8	1
valid_sources[0x67]	50805	1			T1	18		T2	1		T8	5
valid_sources[0x68]	48855	1			T1	5		T2	5		T8	2
valid_sources[0x69]	48782	1			T2	6		T8	3		T9	6
valid_sources[0x6a]	52659	1			T1	1		T2	2		T9	12
valid_sources[0x6b]	58720	1			T1	8		T2	5		T9	1
valid_sources[0x6c]	50890	1			T1	3		T2	12		T8	2
valid_sources[0x6d]	54465	1			T1	9		T2	6		T9	1
valid_sources[0x6e]	48069	1			T2	8		T8	3		T9	1
valid_sources[0x6f]	60747	1			T2	9		T8	3		T9	3
valid_sources[0x70]	56379	1			T5	6505		T8	3		T97	3
valid_sources[0x71]	55453	1			T1	4		T2	2		T8	4
valid_sources[0x72]	49333	1			T1	16		T8	2		T9	9
valid_sources[0x73]	48343	1			T1	3		T2	12		T8	3
valid_sources[0x74]	48202	1			T1	4		T2	1		T9	17
valid_sources[0x75]	52373	1			T2	15		T8	1		T9	2
valid_sources[0x76]	57913	1			T1	3		T8	1		T9	4
valid_sources[0x77]	48457	1			T1	24		T8	7		T9	8
valid_sources[0x78]	84458	1			T1	2		T8	4		T97	3
valid_sources[0x79]	50942	1			T1	8		T2	3		T8	3
valid_sources[0x7a]	49208	1			T1	7		T2	10		T8	3
valid_sources[0x7b]	52263	1			T1	6		T2	4		T8	4
valid_sources[0x7c]	56456	1			T1	2		T8	2		T97	6
valid_sources[0x7d]	54074	1			T1	11		T2	10		T8	4
valid_sources[0x7e]	50805	1			T1	11		T2	11		T8	2
valid_sources[0x7f]	48798	1			T1	24		T8	6		T9	18
valid_sources[0x80]	58616	1			T1	20		T2	2		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3438410

1

T1

450

T2

352

T3

73

values[0x0]

all_enables

biggest_size

1916686

1

T1

48

T2

35

T3

50

values[0x1]

all_enables

biggest_size

1840493

1

T1

32

T2

26

T3

28

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	250012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9030922

1

T1

160

T2

40

T4

500

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2311406	1			T1	80		T2	20		T4	250
values[0x0]	3382411	1			T1	46		T2	10		T4	122
values[0x1]	3587117	1			T1	34		T2	10		T4	128

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90581	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9190353

1

T1

160

T2

40

T4

500

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36075	1			T1	1		T4	1		T5	2
valid_sources[0x01]	35288	1			T5	1		T8	2		T7	350
valid_sources[0x02]	35709	1			T7	495		T61	2		T129	4
valid_sources[0x03]	35841	1			T4	1		T5	1		T15	1
valid_sources[0x04]	37131	1			T4	3		T8	1		T7	345
valid_sources[0x05]	35740	1			T1	1		T4	3		T12	1
valid_sources[0x06]	35460	1			T5	1		T8	2		T7	497
valid_sources[0x07]	36041	1			T1	1		T4	3		T5	1
valid_sources[0x08]	36915	1			T1	2		T7	437		T101	1
valid_sources[0x09]	35475	1			T1	1		T4	7		T5	1
valid_sources[0x0a]	37175	1			T1	2		T12	1		T15	1
valid_sources[0x0b]	36572	1			T1	2		T4	1		T8	2
valid_sources[0x0c]	35889	1			T1	2		T4	1		T5	3
valid_sources[0x0d]	35898	1			T1	1		T5	2		T15	6
valid_sources[0x0e]	35120	1			T1	1		T4	4		T7	470
valid_sources[0x0f]	36214	1			T4	2		T8	2		T12	3
valid_sources[0x10]	37984	1			T4	3		T5	2		T7	375
valid_sources[0x11]	35697	1			T4	4		T5	1		T7	485
valid_sources[0x12]	35486	1			T7	443		T188	1		T61	1
valid_sources[0x13]	37410	1			T1	4		T4	2		T5	2
valid_sources[0x14]	34946	1			T4	1		T8	1		T12	3
valid_sources[0x15]	36691	1			T4	2		T5	1		T8	2
valid_sources[0x16]	36318	1			T1	3		T4	1		T5	1
valid_sources[0x17]	35920	1			T4	8		T5	1		T8	1
valid_sources[0x18]	35879	1			T5	2		T15	5		T7	352
valid_sources[0x19]	36105	1			T1	2		T7	532		T61	2
valid_sources[0x1a]	36266	1			T4	2		T5	1		T15	3
valid_sources[0x1b]	36555	1			T8	3		T7	409		T61	9
valid_sources[0x1c]	37315	1			T1	1		T4	6		T5	1
valid_sources[0x1d]	35285	1			T4	1		T5	1		T7	398
valid_sources[0x1e]	35571	1			T4	1		T5	1		T8	2
valid_sources[0x1f]	36968	1			T8	1		T15	1		T7	572
valid_sources[0x20]	36239	1			T5	1		T8	2		T7	426
valid_sources[0x21]	36191	1			T1	1		T4	1		T12	1
valid_sources[0x22]	34657	1			T4	6		T15	1		T7	419
valid_sources[0x23]	36672	1			T1	1		T4	7		T8	1
valid_sources[0x24]	36096	1			T1	2		T4	8		T5	2
valid_sources[0x25]	36330	1			T5	1		T7	467		T188	9
valid_sources[0x26]	35867	1			T1	1		T7	477		T91	3
valid_sources[0x27]	36919	1			T5	2		T15	5		T7	517
valid_sources[0x28]	36793	1			T1	1		T8	1		T12	1
valid_sources[0x29]	35708	1			T1	1		T4	5		T5	3
valid_sources[0x2a]	36003	1			T4	2		T5	1		T8	1
valid_sources[0x2b]	35978	1			T1	1		T4	4		T5	2
valid_sources[0x2c]	36415	1			T4	1		T5	2		T7	485
valid_sources[0x2d]	36212	1			T12	2		T97	40		T7	511
valid_sources[0x2e]	34933	1			T4	6		T5	2		T7	576
valid_sources[0x2f]	36714	1			T1	1		T4	5		T12	1
valid_sources[0x30]	39113	1			T4	1		T12	1		T15	1
valid_sources[0x31]	35952	1			T1	1		T4	2		T5	2
valid_sources[0x32]	36286	1			T4	2		T5	1		T7	376
valid_sources[0x33]	35249	1			T4	1		T7	460		T61	1
valid_sources[0x34]	35698	1			T4	7		T7	379		T188	2
valid_sources[0x35]	35783	1			T1	1		T4	4		T8	1
valid_sources[0x36]	35292	1			T1	1		T4	1		T5	1
valid_sources[0x37]	35814	1			T4	2		T5	1		T12	3
valid_sources[0x38]	35798	1			T1	1		T4	1		T8	2
valid_sources[0x39]	36237	1			T1	1		T4	1		T5	3
valid_sources[0x3a]	36508	1			T1	1		T5	1		T8	1
valid_sources[0x3b]	37956	1			T1	1		T4	2		T5	1
valid_sources[0x3c]	35886	1			T4	2		T12	1		T7	475
valid_sources[0x3d]	36766	1			T4	3		T5	1		T15	1
valid_sources[0x3e]	36276	1			T4	3		T8	3		T15	1
valid_sources[0x3f]	36339	1			T4	4		T5	2		T7	417
valid_sources[0x40]	36977	1			T4	1		T5	1		T8	1
valid_sources[0x41]	36896	1			T4	4		T15	2		T7	451
valid_sources[0x42]	35917	1			T4	4		T5	2		T9	14
valid_sources[0x43]	35649	1			T1	1		T7	518		T188	4
valid_sources[0x44]	35034	1			T4	2		T12	1		T7	535
valid_sources[0x45]	36261	1			T8	2		T7	455		T91	2
valid_sources[0x46]	36487	1			T1	2		T7	418		T61	2
valid_sources[0x47]	37439	1			T1	1		T8	3		T7	493
valid_sources[0x48]	36097	1			T4	3		T10	2		T12	4
valid_sources[0x49]	36511	1			T9	7		T7	616		T91	2
valid_sources[0x4a]	36736	1			T1	2		T4	1		T5	2
valid_sources[0x4b]	35306	1			T4	3		T8	1		T7	417
valid_sources[0x4c]	35333	1			T4	1		T5	3		T8	1
valid_sources[0x4d]	35685	1			T4	1		T5	1		T8	2
valid_sources[0x4e]	38211	1			T4	2		T5	3		T8	2
valid_sources[0x4f]	36998	1			T1	1		T9	16		T12	3
valid_sources[0x50]	36613	1			T5	1		T8	1		T7	487
valid_sources[0x51]	35779	1			T1	2		T4	4		T5	1
valid_sources[0x52]	36487	1			T1	1		T5	3		T12	4
valid_sources[0x53]	37604	1			T4	1		T5	1		T12	2
valid_sources[0x54]	35901	1			T4	2		T6	2		T7	388
valid_sources[0x55]	34788	1			T4	3		T15	5		T7	442
valid_sources[0x56]	35710	1			T1	1		T4	3		T5	1
valid_sources[0x57]	34676	1			T1	1		T4	1		T8	2
valid_sources[0x58]	35427	1			T1	1		T4	1		T5	2
valid_sources[0x59]	36393	1			T4	2		T8	1		T12	3
valid_sources[0x5a]	36718	1			T4	2		T8	1		T12	2
valid_sources[0x5b]	34934	1			T5	3		T8	1		T12	1
valid_sources[0x5c]	36329	1			T1	1		T4	1		T15	4
valid_sources[0x5d]	36129	1			T1	1		T4	7		T8	1
valid_sources[0x5e]	37154	1			T4	6		T7	492		T91	1
valid_sources[0x5f]	35664	1			T1	1		T4	5		T5	2
valid_sources[0x60]	35647	1			T4	6		T8	2		T7	505
valid_sources[0x61]	35290	1			T1	1		T4	2		T5	1
valid_sources[0x62]	37751	1			T1	2		T5	1		T7	503
valid_sources[0x63]	37161	1			T1	1		T4	4		T12	1
valid_sources[0x64]	37439	1			T1	2		T4	3		T15	1
valid_sources[0x65]	35719	1			T1	1		T4	1		T7	397
valid_sources[0x66]	35881	1			T1	1		T7	493		T61	5
valid_sources[0x67]	35420	1			T4	1		T5	2		T8	3
valid_sources[0x68]	35646	1			T4	4		T6	1		T7	497
valid_sources[0x69]	37587	1			T1	1		T4	4		T5	1
valid_sources[0x6a]	36921	1			T1	1		T4	1		T5	1
valid_sources[0x6b]	35669	1			T4	5		T8	1		T7	421
valid_sources[0x6c]	36450	1			T1	1		T4	1		T12	1
valid_sources[0x6d]	38618	1			T4	2		T15	1		T7	493
valid_sources[0x6e]	34845	1			T4	6		T5	2		T8	2
valid_sources[0x6f]	38280	1			T4	2		T12	1		T15	3
valid_sources[0x70]	35184	1			T4	1		T5	1		T8	1
valid_sources[0x71]	36173	1			T6	2		T7	500		T61	1
valid_sources[0x72]	36617	1			T1	1		T4	3		T5	3
valid_sources[0x73]	36489	1			T1	1		T4	2		T12	2
valid_sources[0x74]	35992	1			T4	4		T12	2		T7	524
valid_sources[0x75]	36439	1			T8	1		T7	542		T188	1
valid_sources[0x76]	35718	1			T1	1		T5	1		T7	393
valid_sources[0x77]	37012	1			T1	2		T4	1		T5	1
valid_sources[0x78]	36157	1			T4	2		T5	1		T8	1
valid_sources[0x79]	34965	1			T1	2		T4	3		T8	1
valid_sources[0x7a]	36690	1			T5	1		T7	462		T61	12
valid_sources[0x7b]	37396	1			T4	4		T12	3		T7	366
valid_sources[0x7c]	36466	1			T1	1		T5	1		T8	3
valid_sources[0x7d]	35678	1			T4	2		T5	2		T8	1
valid_sources[0x7e]	37770	1			T1	2		T4	3		T5	2
valid_sources[0x7f]	37943	1			T1	2		T4	1		T5	2
valid_sources[0x80]	37140	1			T1	1		T4	1		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2297145

1

T1

80

T2

20

T4

250

values[0x0]

all_enables

biggest_size

3365482

1

T1

46

T2

10

T4

122

values[0x1]

all_enables

biggest_size

3368295

1

T1

34

T2

10

T4

128