Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25134951

1

T1

1324

T2

649

T3

301

full_word

8284546

1

T1

530

T2

413

T3

151

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33419197	1			T1	1854		T2	1062		T3	452
auto[TlIntgErrCmd]	103	1			T252	7		T253	4		T254	7
auto[TlIntgErrData]	103	1			T252	7		T253	4		T254	6
auto[TlIntgErrBoth]	94	1			T252	6		T253	2		T254	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9567210

1

T1

1647

T2

914

T3

277

auto[1]

23852287

1

T1

207

T2

148

T3

175

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5995043	1			T1	1197		T2	562		T3	204
auto[TlIntgErrNone]	partial	auto[1]	19139637	1			T1	127		T2	87		T3	97
auto[TlIntgErrNone]	full_word	auto[0]	3572032	1			T1	450		T2	352		T3	73
auto[TlIntgErrNone]	full_word	auto[1]	4712485	1			T1	80		T2	61		T3	78
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T252	3		T253	1		T254	3
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T252	3		T253	2		T254	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T355	2		T356	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T252	1		T253	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T252	3		T253	1		T254	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T252	3		T253	3		T254	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T254	1		T349	1		T352	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T252	1		T358	2		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T254	2		T348	2		T349	6
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T252	5		T253	2		T254	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T357	1		T351	1		T360	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T252	1		T348	1		T350	1