Line Coverage for Module :
prim_mubi8_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Module :
prim_mubi8_sender
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_mubi8_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
2147483647 |
2147483647 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3331194 |
3262110 |
0 |
0 |
T2 |
1460454 |
1440732 |
0 |
0 |
T3 |
784719 |
770469 |
0 |
0 |
T4 |
43185309 |
42903045 |
0 |
0 |
T5 |
4851327 |
4788285 |
0 |
0 |
T8 |
590235 |
576384 |
0 |
0 |
T9 |
980286 |
950646 |
0 |
0 |
T10 |
4474899 |
4381419 |
0 |
0 |
T11 |
769443 |
757017 |
0 |
0 |
T12 |
9520083 |
9430992 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 3 | 50.00 |
CONT_ASSIGN | 34 | 1 | 0 | 0.00 |
CONT_ASSIGN | 48 | 1 | 0 | 0.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
0 |
1 |
48 |
0 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
0 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
486135018 |
485295646 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486135018 |
485295646 |
0 |
0 |
T1 |
58442 |
57230 |
0 |
0 |
T2 |
25622 |
25276 |
0 |
0 |
T3 |
13767 |
13517 |
0 |
0 |
T4 |
757637 |
752685 |
0 |
0 |
T5 |
85111 |
84005 |
0 |
0 |
T8 |
10355 |
10112 |
0 |
0 |
T9 |
17198 |
16678 |
0 |
0 |
T10 |
78507 |
76867 |
0 |
0 |
T11 |
13499 |
13281 |
0 |
0 |
T12 |
167019 |
165456 |
0 |
0 |