Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22331044

1

T1

1041

T2

6362

T3

10411

full_word

7422595

1

T1

262

T2

2191

T3

8184

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29753319	1			T1	1303		T2	8553		T3	18595
auto[TlIntgErrCmd]	103	1			T277	2		T278	9		T279	6
auto[TlIntgErrData]	111	1			T277	3		T278	7		T279	8
auto[TlIntgErrBoth]	106	1			T277	5		T278	4		T279	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8841314

1

T1

1039

T2

7865

T3

16083

auto[1]

20912325

1

T1

264

T2

688

T3

2512

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5569524	1			T1	899		T2	5954		T3	8959
auto[TlIntgErrNone]	partial	auto[1]	16761230	1			T1	142		T2	408		T3	1452
auto[TlIntgErrNone]	full_word	auto[0]	3271654	1			T1	140		T2	1911		T3	7124
auto[TlIntgErrNone]	full_word	auto[1]	4150911	1			T1	122		T2	280		T3	1060
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T278	3		T279	2		T283	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T277	2		T278	6		T279	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T388	1		T389	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T390	1		T391	1		T392	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T277	1		T278	3		T279	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T277	2		T278	4		T279	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T279	1		T283	2		T285	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T283	1		T285	1		T393	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T278	1		T279	3		T283	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T277	5		T278	3		T279	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T394	1		T386	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T283	1		T285	1		T391	1