Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.21 98.59 85.95 92.31 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter_sram 98.64 100.00 94.55 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter_sram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.64 100.00 94.55 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.03 89.71 92.65 89.77 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.97 98.05 96.15 97.02 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 91.36 95.00 87.10 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 92.37 95.00 89.47 85.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 91.36 95.00 87.10 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL717098.59
CONT_ASSIGN10400
CONT_ASSIGN11100
ALWAYS12633100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN26211100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
ALWAYS2698787.50
ALWAYS28966100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30711100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33711100.00
CONT_ASSIGN34911100.00
ALWAYS35233100.00
CONT_ASSIGN35911100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38111100.00
CONT_ASSIGN38211100.00
ALWAYS41266100.00
ALWAYS42455100.00
CONT_ASSIGN43911100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44111100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44811100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN47311100.00
ALWAYS49133100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50011100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
104 unreachable
111 unreachable
126 1 1
127 1 1
128 1 1
129 unreachable
MISSING_ELSE
135 1 1
141 1 1
148 1 1
153 1 1
173 1 1
185 1 1
262 1 1
263 1 1
264 1 1
269 1 1
271 1 1
272 1 1
274 1 1
275 1 1
276 1 1
279 0 1
282 1 1
289 1 1
291 1 1
292 1 1
293 1 1
295 1 1
298 1 1
303 1 1
307 1 1
326 1 1
331 1 1
337 1 1
349 1 1
352 1 1
353 1 1
355 1 1
359 1 1
379 1 1
380 1 1
381 1 1
382 1 1
412 1 1
413 1 1
415 1 1
416 1 1
417 1 1
418 1 1
MISSING_ELSE
424 1 1
425 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
439 1 1
440 1 1
441 1 1
445 1 1
446 1 1
448 1 1
449 1 1
456 1 1
459 1 1
463 1 1
464 1 1
466 1 1
473 1 1
491 1 1
492 1 1
493 1 1
497 1 1
500 1 1
505 1 1
510 1 1


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions12110485.95
Logical12110485.95
Non-Logical00
Event00

 LINE       111
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       128
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       135
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       141
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T12,T102
10CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       153
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       173
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000CoveredT5,T6,T13
100000Not Covered

 LINE       262
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT5,T6,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       263
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T9
11CoveredT1,T2,T3

 LINE       264
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       275
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       292
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT5,T6,T13
1CoveredT1,T2,T3

 LINE       293
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T13
10CoveredT2,T3,T4

 LINE       303
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT5,T6,T13
1110Not Covered
1111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       331
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       331
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT5,T6,T13
10CoveredT1,T2,T3
11Not Covered

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT5,T6,T13
111CoveredT5,T6,T13

 LINE       359
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T13

 LINE       359
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT5,T6,T13

 LINE       359
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       359
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       359
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT139,T111,T270
110Not Covered
111CoveredT1,T2,T3

 LINE       359
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T13
10CoveredT1,T2,T3

 LINE       379
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT5,T6,T13
111CoveredT1,T2,T3

 LINE       381
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT5,T6,T13

 LINE       382
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       418
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T13

 LINE       418
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT5,T6,T13
10CoveredT1,T2,T3
11CoveredT5,T6,T13

 LINE       441
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT5,T26,T6
11CoveredT1,T2,T3

 LINE       449
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       463
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       466
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       505
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       505
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T13
11CoveredT1,T2,T3

 LINE       505
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 24 92.31
TERNARY 141 2 2 100.00
TERNARY 331 2 2 100.00
TERNARY 337 3 2 66.67
TERNARY 382 2 2 100.00
TERNARY 505 2 2 100.00
IF 126 2 2 100.00
IF 271 4 3 75.00
IF 291 3 3 100.00
IF 352 2 2 100.00
IF 415 2 2 100.00
IF 427 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 141 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 331 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 337 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 382 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 505 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 126 if ((!rst_ni)) -2-: 128 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 271 if (reqfifo_rvalid) -2-: 272 if (reqfifo_rdata.error) -3-: 275 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T5,T6,T13
1 0 1 Covered T1,T2,T3
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 291 if (reqfifo_rvalid) -2-: 292 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T5,T6,T13
0 - Covered T1,T2,T3


LineNo. Expression -1-: 352 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 415 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 427 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 440204013 439348988 0 0
DataIntgOptions_A 1142 1142 0 0
ReqOutKnown_A 440204013 439348988 0 0
SramDwHasByteGranularity_A 1142 1142 0 0
SramDwIsMultipleOfTlulWidth_A 1142 1142 0 0
TlOutKnownIfFifoKnown_A 440204013 439348988 0 0
TlOutValidKnown_A 440204013 439348988 0 0
WdataOutKnown_A 440204013 439348988 0 0
WeOutKnown_A 440204013 439348988 0 0
WmaskOutKnown_A 440204013 439348988 0 0
adapterNoReadOrWrite 1142 1142 0 0
rvalidHighReqFifoEmpty 440204013 98584 0 0
rvalidHighWhenRspFifoFull 440204013 98584 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 98584 0 0
T1 12865 20 0 0
T2 67375 28 0 0
T3 285796 144 0 0
T4 60246 44 0 0
T5 707829 426 0 0
T8 8860 20 0 0
T9 55873 1 0 0
T10 24037 8 0 0
T11 11548 20 0 0
T12 26377 1 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 98584 0 0
T1 12865 20 0 0
T2 67375 28 0 0
T3 285796 144 0 0
T4 60246 44 0 0
T5 707829 426 0 0
T8 8860 20 0 0
T9 55873 1 0 0
T10 24037 8 0 0
T11 11548 20 0 0
T12 26377 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL7070100.00
CONT_ASSIGN10400
CONT_ASSIGN11100
ALWAYS12633100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN26211100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
ALWAYS26977100.00
ALWAYS28966100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30711100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33711100.00
CONT_ASSIGN34911100.00
ALWAYS35233100.00
CONT_ASSIGN35911100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38111100.00
CONT_ASSIGN38211100.00
ALWAYS41266100.00
ALWAYS42455100.00
CONT_ASSIGN43911100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44111100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44811100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN47311100.00
ALWAYS49133100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50011100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
104 unreachable
111 unreachable
126 1 1
127 1 1
128 1 1
129 unreachable
MISSING_ELSE
135 1 1
141 1 1
148 1 1
153 1 1
173 1 1
185 1 1
262 1 1
263 1 1
264 1 1
269 1 1
271 1 1
272 1 1
274 1 1
275 1 1
276 1 1
279 excluded
Exclude Annotation: VC_COV_UNR
282 1 1
289 1 1
291 1 1
292 1 1
293 1 1
295 1 1
298 1 1
303 1 1
307 1 1
326 1 1
331 1 1
337 1 1
349 1 1
352 1 1
353 1 1
355 1 1
359 1 1
379 1 1
380 1 1
381 1 1
382 1 1
412 1 1
413 1 1
415 1 1
416 1 1
417 1 1
418 1 1
MISSING_ELSE
424 1 1
425 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
439 1 1
440 1 1
441 1 1
445 1 1
446 1 1
448 1 1
449 1 1
456 1 1
459 1 1
463 1 1
464 1 1
466 1 1
473 1 1
491 1 1
492 1 1
493 1 1
497 1 1
500 1 1
505 1 1
510 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram
TotalCoveredPercent
Conditions11010494.55
Logical11010494.55
Non-Logical00
Event00

 LINE       111
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       128
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       135
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       141
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T12,T102
10CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       153
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       173
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTestsExclude Annotation
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000CoveredT5,T6,T13
100000Excluded VC_COV_UNR

 LINE       262
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT5,T6,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       263
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T9
11CoveredT1,T2,T3

 LINE       264
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT1,T2,T3

 LINE       275
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3

 LINE       292
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT5,T6,T13
1CoveredT1,T2,T3

 LINE       293
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T13
10CoveredT2,T3,T4

 LINE       303
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTestsExclude Annotation
0111Excluded VC_COV_UNR
1011Excluded VC_COV_UNR
1101CoveredT5,T6,T13
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       331
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       331
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTestsExclude Annotation
01CoveredT5,T6,T13
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT5,T6,T13
111CoveredT5,T6,T13

 LINE       359
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T13

 LINE       359
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT5,T6,T13

 LINE       359
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       359
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       359
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT139,T111,T270
110Not Covered
111CoveredT1,T2,T3

 LINE       359
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T13
10CoveredT1,T2,T3

 LINE       379
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT5,T6,T13
111CoveredT1,T2,T3

 LINE       381
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT5,T6,T13

 LINE       382
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       418
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T13

 LINE       418
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT5,T6,T13
10CoveredT1,T2,T3
11CoveredT5,T6,T13

 LINE       441
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTestsExclude Annotation
01Excluded vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR
10CoveredT5,T26,T6
11CoveredT1,T2,T3

 LINE       449
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       463
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       466
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       505
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       505
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T13
11CoveredT1,T2,T3

 LINE       505
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 141 2 2 100.00
TERNARY 331 2 2 100.00
TERNARY 337 2 2 100.00
TERNARY 382 2 2 100.00
TERNARY 505 2 2 100.00
IF 126 2 2 100.00
IF 271 3 3 100.00
IF 291 3 3 100.00
IF 352 2 2 100.00
IF 415 2 2 100.00
IF 427 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 141 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 331 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 337 (vld_rd_rsp) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Excluded VC_COV_UNR
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 382 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 505 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 126 if ((!rst_ni)) -2-: 128 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 271 if (reqfifo_rvalid) -2-: 272 if (reqfifo_rdata.error) -3-: 275 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTestsExclude Annotation
1 1 - Covered T5,T6,T13
1 0 1 Covered T1,T2,T3
1 0 0 Excluded VC_COV_UNR
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 291 if (reqfifo_rvalid) -2-: 292 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T5,T6,T13
0 - Covered T1,T2,T3


LineNo. Expression -1-: 352 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 415 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 427 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 440204013 439348988 0 0
DataIntgOptions_A 1142 1142 0 0
ReqOutKnown_A 440204013 439348988 0 0
SramDwHasByteGranularity_A 1142 1142 0 0
SramDwIsMultipleOfTlulWidth_A 1142 1142 0 0
TlOutKnownIfFifoKnown_A 440204013 439348988 0 0
TlOutValidKnown_A 440204013 439348988 0 0
WdataOutKnown_A 440204013 439348988 0 0
WeOutKnown_A 440204013 439348988 0 0
WmaskOutKnown_A 440204013 439348988 0 0
adapterNoReadOrWrite 1142 1142 0 0
rvalidHighReqFifoEmpty 440204013 98584 0 0
rvalidHighWhenRspFifoFull 440204013 98584 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 439348988 0 0
T1 12865 12611 0 0
T2 67375 66053 0 0
T3 285796 283637 0 0
T4 60246 59426 0 0
T5 707829 707815 0 0
T8 8860 8665 0 0
T9 55873 55157 0 0
T10 24037 23532 0 0
T11 11548 11286 0 0
T12 26377 25875 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1142 1142 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 98584 0 0
T1 12865 20 0 0
T2 67375 28 0 0
T3 285796 144 0 0
T4 60246 44 0 0
T5 707829 426 0 0
T8 8860 20 0 0
T9 55873 1 0 0
T10 24037 8 0 0
T11 11548 20 0 0
T12 26377 1 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 440204013 98584 0 0
T1 12865 20 0 0
T2 67375 28 0 0
T3 285796 144 0 0
T4 60246 44 0 0
T5 707829 426 0 0
T8 8860 20 0 0
T9 55873 1 0 0
T10 24037 8 0 0
T11 11548 20 0 0
T12 26377 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%