Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	98.05	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	443305161	7085623	0	0
check_regwen_rd_A	443305161	3474	0	0
check_timeout_rd_A	443305161	2662	0	0
check_trigger_regwen_rd_A	443305161	3568	0	0
consistency_check_period_rd_A	443305161	3711	0	0
creator_sw_cfg_read_lock_rd_A	443305161	2704	0	0
direct_access_address_rd_A	443305161	2155	0	0
direct_access_wdata_0_rd_A	443305161	1485	0	0
direct_access_wdata_1_rd_A	443305161	1763	0	0
integrity_check_period_rd_A	443305161	3577	0	0
intr_enable_rd_A	443305161	4600	0	0
owner_sw_cfg_read_lock_rd_A	443305161	2241	0	0
rot_creator_auth_codesign_read_lock_rd_A	443305161	2826	0	0
rot_creator_auth_state_read_lock_rd_A	443305161	2383	0	0
vendor_test_read_lock_rd_A	443305161	2617	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	7085623	0	0
T5	707829	154277	0	0
T6	0	86264	0	0
T9	55873	0	0	0
T10	24037	0	0	0
T11	11548	0	0	0
T12	26377	0	0	0
T13	0	140511	0	0
T14	0	11197	0	0
T16	0	64414	0	0
T30	12349	0	0	0
T67	11052	0	0	0
T77	9268	0	0	0
T102	11973	0	0	0
T106	11982	0	0	0
T111	0	244378	0	0
T113	0	143285	0	0
T137	0	120135	0	0
T139	0	67435	0	0
T266	0	68131	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	3474	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	252	0	0
T124	19050	0	0	0
T139	336600	95	0	0
T151	39097	0	0	0
T161	0	34	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	49	0	0
T255	0	57	0	0
T264	10813	0	0	0
T270	0	36	0	0
T367	0	95	0	0
T368	0	46	0	0
T369	0	34	0	0
T370	0	46	0	0
T371	11073	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	2662	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	375	0	0
T124	19050	0	0	0
T139	336600	67	0	0
T151	39097	0	0	0
T161	0	23	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	62	0	0
T255	0	61	0	0
T264	10813	0	0	0
T270	0	47	0	0
T367	0	108	0	0
T368	0	52	0	0
T369	0	52	0	0
T370	0	46	0	0
T371	11073	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	3568	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	293	0	0
T124	19050	0	0	0
T139	336600	58	0	0
T151	39097	0	0	0
T161	0	17	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	13	0	0
T255	0	60	0	0
T264	10813	0	0	0
T270	0	63	0	0
T367	0	63	0	0
T368	0	39	0	0
T369	0	39	0	0
T370	0	65	0	0
T371	11073	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	3711	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	320	0	0
T124	19050	0	0	0
T139	336600	105	0	0
T151	39097	0	0	0
T161	0	24	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	31	0	0
T255	0	68	0	0
T264	10813	0	0	0
T270	0	47	0	0
T367	0	121	0	0
T368	0	35	0	0
T369	0	33	0	0
T370	0	54	0	0
T371	11073	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	2704	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	252	0	0
T124	19050	0	0	0
T139	336600	75	0	0
T151	39097	0	0	0
T161	0	13	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	33	0	0
T255	0	69	0	0
T264	10813	0	0	0
T270	0	69	0	0
T367	0	145	0	0
T368	0	53	0	0
T369	0	48	0	0
T370	0	54	0	0
T371	11073	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	2155	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	262	0	0
T124	19050	0	0	0
T139	336600	90	0	0
T151	39097	0	0	0
T161	0	33	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	69	0	0
T255	0	36	0	0
T264	10813	0	0	0
T270	0	50	0	0
T367	0	119	0	0
T368	0	61	0	0
T369	0	40	0	0
T370	0	82	0	0
T371	11073	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	1485	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	195	0	0
T124	19050	0	0	0
T139	336600	54	0	0
T151	39097	0	0	0
T161	0	20	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	25	0	0
T255	0	50	0	0
T264	10813	0	0	0
T270	0	72	0	0
T367	0	94	0	0
T368	0	26	0	0
T369	0	29	0	0
T370	0	46	0	0
T371	11073	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	1763	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	275	0	0
T124	19050	0	0	0
T139	336600	69	0	0
T151	39097	0	0	0
T161	0	12	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	42	0	0
T255	0	48	0	0
T264	10813	0	0	0
T270	0	24	0	0
T367	0	79	0	0
T368	0	62	0	0
T369	0	31	0	0
T370	0	59	0	0
T371	11073	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	3577	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	254	0	0
T124	19050	0	0	0
T139	336600	67	0	0
T151	39097	0	0	0
T161	0	29	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	51	0	0
T255	0	86	0	0
T264	10813	0	0	0
T270	0	79	0	0
T367	0	138	0	0
T368	0	47	0	0
T369	0	44	0	0
T370	0	33	0	0
T371	11073	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	4600	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T101	0	15	0	0
T111	0	290	0	0
T124	19050	0	0	0
T139	336600	89	0	0
T151	39097	0	0	0
T161	0	27	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	56	0	0
T255	0	65	0	0
T264	10813	0	0	0
T270	0	38	0	0
T367	0	86	0	0
T368	0	44	0	0
T369	0	33	0	0
T371	11073	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	2241	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	287	0	0
T124	19050	0	0	0
T139	336600	59	0	0
T151	39097	0	0	0
T161	0	11	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	30	0	0
T255	0	39	0	0
T264	10813	0	0	0
T270	0	39	0	0
T367	0	80	0	0
T368	0	37	0	0
T369	0	24	0	0
T370	0	51	0	0
T371	11073	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	2826	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	215	0	0
T124	19050	0	0	0
T139	336600	55	0	0
T151	39097	0	0	0
T161	0	24	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	32	0	0
T255	0	91	0	0
T264	10813	0	0	0
T270	0	67	0	0
T367	0	96	0	0
T368	0	50	0	0
T369	0	44	0	0
T370	0	87	0	0
T371	11073	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	2383	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	237	0	0
T124	19050	0	0	0
T139	336600	57	0	0
T151	39097	0	0	0
T161	0	20	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	28	0	0
T255	0	62	0	0
T264	10813	0	0	0
T270	0	57	0	0
T367	0	80	0	0
T368	0	67	0	0
T369	0	33	0	0
T370	0	40	0	0
T371	11073	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443305161	2617	0	0
T59	209019	0	0	0
T66	10847	0	0	0
T98	39642	0	0	0
T111	0	247	0	0
T124	19050	0	0	0
T139	336600	118	0	0
T151	39097	0	0	0
T161	0	39	0	0
T228	10892	0	0	0
T237	63382	0	0	0
T239	0	26	0	0
T255	0	36	0	0
T264	10813	0	0	0
T270	0	41	0	0
T367	0	113	0	0
T368	0	42	0	0
T369	0	11	0	0
T370	0	74	0	0
T371	11073	0	0	0