Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6937473	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6857534

1

T1

177

T2

189

T3

722

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8019169	1			T1	326		T2	783		T3	1037
values[0x0]	2197734	1			T1	106		T2	118		T3	329
values[0x1]	3578104	1			T1	114		T2	109		T3	347

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4497152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9297855

1

T1

266

T2

427

T3

940

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54329	1			T1	5		T4	29		T5	2
valid_sources[0x01]	54680	1			T3	6		T5	24		T10	2
valid_sources[0x02]	48920	1			T1	2		T3	4		T4	6
valid_sources[0x03]	53435	1			T1	2		T3	4		T4	16
valid_sources[0x04]	48083	1			T1	2		T4	6		T5	9
valid_sources[0x05]	48527	1			T1	2		T3	5		T5	6
valid_sources[0x06]	47417	1			T1	2		T3	2		T4	29
valid_sources[0x07]	51544	1			T3	19		T10	3		T11	1
valid_sources[0x08]	57283	1			T1	2		T4	1		T10	6
valid_sources[0x09]	49688	1			T1	2		T3	10		T5	4
valid_sources[0x0a]	47948	1			T1	3		T5	3		T10	2
valid_sources[0x0b]	91191	1			T1	4		T10	3		T11	4
valid_sources[0x0c]	46702	1			T1	6		T3	12		T5	8
valid_sources[0x0d]	49250	1			T1	2		T3	8		T4	34
valid_sources[0x0e]	46912	1			T3	8		T4	31		T5	1
valid_sources[0x0f]	54596	1			T1	2		T3	6		T10	6
valid_sources[0x10]	53259	1			T1	4		T4	22		T5	13
valid_sources[0x11]	51790	1			T1	2		T3	11		T5	6
valid_sources[0x12]	48787	1			T1	2		T5	5		T10	3
valid_sources[0x13]	49850	1			T1	3		T3	1		T5	6
valid_sources[0x14]	47610	1			T1	4		T3	3		T4	15
valid_sources[0x15]	48441	1			T1	1		T3	14		T4	14
valid_sources[0x16]	63064	1			T1	2		T3	2		T5	5
valid_sources[0x17]	49306	1			T3	9		T11	2		T6	41
valid_sources[0x18]	48278	1			T5	4		T10	1		T11	2
valid_sources[0x19]	56473	1			T1	1		T3	3		T4	8
valid_sources[0x1a]	64741	1			T1	2		T3	10		T4	14
valid_sources[0x1b]	52662	1			T1	1		T3	17		T5	6
valid_sources[0x1c]	127265	1			T1	5		T3	15		T5	3
valid_sources[0x1d]	58531	1			T4	47		T5	4		T10	10
valid_sources[0x1e]	133017	1			T1	1		T10	17		T11	1
valid_sources[0x1f]	48787	1			T1	4		T3	7		T4	65
valid_sources[0x20]	49315	1			T1	1		T3	1		T5	9
valid_sources[0x21]	47637	1			T1	3		T3	4		T10	4
valid_sources[0x22]	47570	1			T1	1		T3	7		T10	3
valid_sources[0x23]	51715	1			T1	2		T3	2		T5	12
valid_sources[0x24]	51894	1			T1	2		T3	29		T4	12
valid_sources[0x25]	58045	1			T1	4		T3	3		T4	1
valid_sources[0x26]	57804	1			T1	2		T3	3		T4	15
valid_sources[0x27]	46726	1			T1	4		T3	11		T5	4
valid_sources[0x28]	52776	1			T3	1		T4	15		T5	7
valid_sources[0x29]	47589	1			T3	28		T5	5		T10	4
valid_sources[0x2a]	52591	1			T3	2		T4	11		T5	1
valid_sources[0x2b]	47700	1			T1	4		T3	19		T4	27
valid_sources[0x2c]	49230	1			T1	2		T3	2		T4	19
valid_sources[0x2d]	56768	1			T1	1		T3	1		T4	18
valid_sources[0x2e]	63671	1			T1	3		T3	9		T4	19
valid_sources[0x2f]	47857	1			T1	1		T3	7		T4	10
valid_sources[0x30]	51410	1			T1	1		T4	40		T5	6
valid_sources[0x31]	50204	1			T3	5		T4	25		T5	2
valid_sources[0x32]	50596	1			T1	1		T3	22		T5	1
valid_sources[0x33]	48439	1			T3	9		T4	8		T10	1
valid_sources[0x34]	63904	1			T1	1		T3	4		T4	4
valid_sources[0x35]	58934	1			T1	1		T3	2		T4	5
valid_sources[0x36]	47161	1			T1	5		T3	8		T4	6
valid_sources[0x37]	53447	1			T1	3		T3	15		T11	2
valid_sources[0x38]	55920	1			T1	5		T3	1		T4	93
valid_sources[0x39]	59571	1			T3	10		T5	15		T10	1
valid_sources[0x3a]	50903	1			T1	4		T6	258		T7	7
valid_sources[0x3b]	61220	1			T1	4		T5	7		T11	2
valid_sources[0x3c]	46944	1			T1	4		T5	1		T10	2
valid_sources[0x3d]	49464	1			T1	3		T3	8		T10	5
valid_sources[0x3e]	51022	1			T1	2		T5	7		T10	4
valid_sources[0x3f]	57676	1			T3	10		T10	2		T11	1
valid_sources[0x40]	47982	1			T4	33		T5	8		T11	9
valid_sources[0x41]	48424	1			T3	34		T11	2		T6	277
valid_sources[0x42]	51965	1			T1	1		T3	2		T5	5
valid_sources[0x43]	62758	1			T1	4		T6	307		T7	6
valid_sources[0x44]	50276	1			T1	4		T4	4		T10	2
valid_sources[0x45]	52389	1			T1	5		T3	16		T4	1
valid_sources[0x46]	50501	1			T1	2		T3	25		T5	5
valid_sources[0x47]	48293	1			T1	4		T3	2		T10	8
valid_sources[0x48]	55686	1			T1	2		T3	9		T10	3
valid_sources[0x49]	63862	1			T1	4		T3	15		T4	11
valid_sources[0x4a]	55198	1			T1	5		T3	25		T5	8
valid_sources[0x4b]	46488	1			T1	2		T5	9		T11	2
valid_sources[0x4c]	55307	1			T1	1		T3	11		T5	4
valid_sources[0x4d]	47289	1			T1	2		T3	9		T4	15
valid_sources[0x4e]	59507	1			T1	3		T3	2		T4	24
valid_sources[0x4f]	48278	1			T1	2		T3	6		T11	4
valid_sources[0x50]	48432	1			T1	2		T3	1		T10	1
valid_sources[0x51]	47990	1			T1	1		T3	21		T4	25
valid_sources[0x52]	47654	1			T1	2		T10	8		T11	2
valid_sources[0x53]	47270	1			T1	2		T3	31		T4	24
valid_sources[0x54]	50145	1			T3	4		T10	8		T6	205
valid_sources[0x55]	52035	1			T3	32		T4	8		T5	1
valid_sources[0x56]	48293	1			T1	1		T3	3		T5	4
valid_sources[0x57]	47789	1			T1	8		T3	12		T5	18
valid_sources[0x58]	49587	1			T1	1		T3	8		T4	41
valid_sources[0x59]	50814	1			T1	1		T3	4		T4	22
valid_sources[0x5a]	48370	1			T1	2		T3	3		T4	33
valid_sources[0x5b]	48650	1			T1	1		T3	6		T5	2
valid_sources[0x5c]	47372	1			T1	6		T3	2		T5	1
valid_sources[0x5d]	51714	1			T1	3		T3	1		T5	1
valid_sources[0x5e]	50069	1			T1	1		T3	9		T5	8
valid_sources[0x5f]	59738	1			T1	10		T3	3		T5	8
valid_sources[0x60]	48438	1			T3	18		T4	13		T10	4
valid_sources[0x61]	54634	1			T3	1		T10	1		T11	1
valid_sources[0x62]	60975	1			T1	7		T5	4		T10	1
valid_sources[0x63]	100987	1			T1	2		T3	22		T10	4
valid_sources[0x64]	48107	1			T1	6		T4	31		T5	8
valid_sources[0x65]	50994	1			T1	2		T3	1		T4	4
valid_sources[0x66]	51072	1			T5	9		T10	4		T11	3
valid_sources[0x67]	48110	1			T1	3		T3	5		T4	18
valid_sources[0x68]	49225	1			T1	2		T5	15		T10	1
valid_sources[0x69]	50985	1			T3	1		T10	1		T11	10
valid_sources[0x6a]	49153	1			T10	3		T6	213		T7	7
valid_sources[0x6b]	54253	1			T1	1		T3	6		T4	10
valid_sources[0x6c]	47612	1			T1	3		T3	1		T4	15
valid_sources[0x6d]	53641	1			T1	2		T5	8		T10	3
valid_sources[0x6e]	61964	1			T1	3		T3	9		T4	17
valid_sources[0x6f]	48567	1			T2	1010		T3	4		T11	4
valid_sources[0x70]	49457	1			T1	1		T3	3		T5	15
valid_sources[0x71]	53132	1			T1	6		T3	5		T4	10
valid_sources[0x72]	57537	1			T1	1		T10	2		T6	458
valid_sources[0x73]	51810	1			T1	1		T4	1		T10	1
valid_sources[0x74]	61534	1			T1	3		T3	13		T5	1
valid_sources[0x75]	47795	1			T3	3		T5	4		T10	1
valid_sources[0x76]	60288	1			T1	3		T3	3		T4	15
valid_sources[0x77]	49056	1			T1	2		T3	4		T4	11
valid_sources[0x78]	48194	1			T1	1		T4	70		T5	1
valid_sources[0x79]	51609	1			T1	1		T3	9		T5	8
valid_sources[0x7a]	50745	1			T1	5		T3	17		T5	2
valid_sources[0x7b]	49352	1			T1	3		T3	23		T4	5
valid_sources[0x7c]	48816	1			T1	3		T5	13		T10	1
valid_sources[0x7d]	49011	1			T1	1		T3	4		T4	43
valid_sources[0x7e]	48623	1			T1	2		T3	4		T5	9
valid_sources[0x7f]	48476	1			T1	5		T3	8		T4	11
valid_sources[0x80]	50252	1			T1	1		T3	1		T4	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3283830

1

T1

89

T2

97

T3

451

values[0x0]

all_enables

biggest_size

1823881

1

T1

42

T2

56

T3

159

values[0x1]

all_enables

biggest_size

1749823

1

T1

46

T2

36

T3

112

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	239515	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8584644

1

T3

140

T4

40

T6

53828

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2195896	1			T3	70		T4	20		T6	13556
values[0x0]	3218414	1			T3	38		T4	9		T6	20054
values[0x1]	3409849	1			T3	32		T4	11		T6	21581

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	86949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8737210

1

T3

140

T4

40

T6

54719

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34116	1			T3	1		T4	1		T6	229
valid_sources[0x01]	34810	1			T6	203		T15	1		T9	249
valid_sources[0x02]	34569	1			T6	169		T9	227		T119	1
valid_sources[0x03]	35361	1			T3	3		T6	231		T9	234
valid_sources[0x04]	35276	1			T3	1		T4	1		T6	181
valid_sources[0x05]	34272	1			T3	2		T6	213		T72	2
valid_sources[0x06]	34777	1			T6	174		T31	2		T9	251
valid_sources[0x07]	35218	1			T3	1		T6	244		T31	1
valid_sources[0x08]	35783	1			T6	227		T72	4		T9	239
valid_sources[0x09]	34235	1			T3	1		T4	2		T6	246
valid_sources[0x0a]	36057	1			T6	201		T113	1		T31	1
valid_sources[0x0b]	35133	1			T3	1		T6	202		T31	1
valid_sources[0x0c]	34242	1			T6	217		T9	239		T71	4
valid_sources[0x0d]	34918	1			T6	225		T9	231		T118	20
valid_sources[0x0e]	33738	1			T3	2		T6	216		T31	1
valid_sources[0x0f]	36040	1			T6	226		T31	3		T9	230
valid_sources[0x10]	33637	1			T6	218		T9	232		T119	2
valid_sources[0x11]	33490	1			T6	198		T31	1		T9	249
valid_sources[0x12]	35717	1			T6	214		T113	2		T9	269
valid_sources[0x13]	33994	1			T6	198		T9	222		T71	1
valid_sources[0x14]	33434	1			T3	2		T6	220		T31	3
valid_sources[0x15]	34135	1			T4	2		T6	196		T113	2
valid_sources[0x16]	33867	1			T3	1		T4	1		T6	232
valid_sources[0x17]	33910	1			T3	1		T6	266		T72	2
valid_sources[0x18]	32591	1			T3	1		T6	259		T9	224
valid_sources[0x19]	34160	1			T3	1		T6	218		T31	1
valid_sources[0x1a]	35311	1			T6	211		T31	1		T9	212
valid_sources[0x1b]	35098	1			T6	254		T72	13		T113	1
valid_sources[0x1c]	35748	1			T3	1		T6	212		T72	6
valid_sources[0x1d]	35103	1			T6	194		T31	1		T9	255
valid_sources[0x1e]	33690	1			T6	210		T72	7		T113	2
valid_sources[0x1f]	34644	1			T3	1		T6	255		T31	1
valid_sources[0x20]	34377	1			T3	1		T4	1		T6	216
valid_sources[0x21]	34504	1			T6	231		T9	230		T14	7
valid_sources[0x22]	33168	1			T6	227		T15	1		T113	2
valid_sources[0x23]	34552	1			T6	189		T31	3		T9	234
valid_sources[0x24]	34969	1			T6	264		T12	4		T9	241
valid_sources[0x25]	33520	1			T6	226		T9	245		T125	1
valid_sources[0x26]	33424	1			T3	5		T6	235		T9	210
valid_sources[0x27]	33813	1			T6	201		T9	213		T14	5
valid_sources[0x28]	33555	1			T3	1		T6	203		T42	12
valid_sources[0x29]	33873	1			T3	1		T4	1		T6	188
valid_sources[0x2a]	34666	1			T6	198		T15	1		T31	1
valid_sources[0x2b]	35250	1			T3	2		T6	202		T31	1
valid_sources[0x2c]	34635	1			T3	1		T6	186		T9	229
valid_sources[0x2d]	34328	1			T6	226		T9	220		T105	1
valid_sources[0x2e]	33998	1			T3	1		T6	209		T72	1
valid_sources[0x2f]	34200	1			T4	1		T6	225		T31	2
valid_sources[0x30]	34207	1			T3	2		T6	221		T113	1
valid_sources[0x31]	33881	1			T6	232		T9	230		T119	2
valid_sources[0x32]	35415	1			T6	222		T9	204		T119	3
valid_sources[0x33]	34335	1			T3	1		T6	185		T9	254
valid_sources[0x34]	36812	1			T6	195		T72	3		T9	267
valid_sources[0x35]	35294	1			T4	1		T6	247		T31	1
valid_sources[0x36]	35059	1			T3	1		T4	1		T6	253
valid_sources[0x37]	32918	1			T3	1		T6	203		T72	2
valid_sources[0x38]	34221	1			T3	2		T6	229		T16	120
valid_sources[0x39]	35163	1			T6	214		T72	3		T9	212
valid_sources[0x3a]	33783	1			T6	170		T72	9		T15	1
valid_sources[0x3b]	33914	1			T6	266		T72	4		T31	1
valid_sources[0x3c]	34389	1			T6	202		T9	209		T18	1
valid_sources[0x3d]	33608	1			T6	227		T15	1		T113	1
valid_sources[0x3e]	35177	1			T6	218		T9	224		T14	5
valid_sources[0x3f]	34697	1			T6	180		T31	1		T9	214
valid_sources[0x40]	34224	1			T3	1		T6	223		T9	225
valid_sources[0x41]	34774	1			T6	200		T113	6		T9	219
valid_sources[0x42]	33927	1			T3	1		T6	228		T31	1
valid_sources[0x43]	33133	1			T3	2		T6	192		T12	2
valid_sources[0x44]	35293	1			T6	219		T9	232		T139	1
valid_sources[0x45]	34673	1			T6	209		T9	237		T119	3
valid_sources[0x46]	34203	1			T3	1		T6	220		T72	2
valid_sources[0x47]	34144	1			T6	253		T31	1		T9	220
valid_sources[0x48]	34262	1			T3	2		T6	201		T31	1
valid_sources[0x49]	34658	1			T6	204		T72	1		T15	3
valid_sources[0x4a]	33955	1			T6	192		T72	10		T31	1
valid_sources[0x4b]	33172	1			T3	2		T6	167		T72	2
valid_sources[0x4c]	34636	1			T6	137		T31	1		T9	230
valid_sources[0x4d]	34378	1			T6	194		T72	1		T31	1
valid_sources[0x4e]	33654	1			T6	259		T9	241		T18	4
valid_sources[0x4f]	33612	1			T3	2		T6	218		T9	230
valid_sources[0x50]	35326	1			T6	234		T9	277		T119	1
valid_sources[0x51]	35344	1			T4	1		T6	180		T113	2
valid_sources[0x52]	34907	1			T6	249		T9	247		T119	1
valid_sources[0x53]	33646	1			T6	234		T72	1		T9	223
valid_sources[0x54]	33756	1			T6	242		T72	9		T9	242
valid_sources[0x55]	33645	1			T6	163		T72	3		T9	242
valid_sources[0x56]	33875	1			T6	199		T15	1		T9	244
valid_sources[0x57]	35078	1			T6	195		T72	1		T9	215
valid_sources[0x58]	34513	1			T6	193		T72	1		T31	1
valid_sources[0x59]	34420	1			T3	1		T6	203		T113	3
valid_sources[0x5a]	35409	1			T6	267		T31	1		T9	240
valid_sources[0x5b]	34323	1			T3	3		T6	225		T113	1
valid_sources[0x5c]	32576	1			T3	2		T4	1		T6	268
valid_sources[0x5d]	35153	1			T6	214		T113	4		T9	251
valid_sources[0x5e]	34316	1			T3	1		T6	189		T113	1
valid_sources[0x5f]	34427	1			T6	174		T9	238		T119	1
valid_sources[0x60]	34799	1			T6	217		T72	4		T31	1
valid_sources[0x61]	35277	1			T6	208		T113	1		T9	237
valid_sources[0x62]	33964	1			T6	240		T9	214		T119	1
valid_sources[0x63]	34896	1			T6	229		T72	6		T9	225
valid_sources[0x64]	37200	1			T3	1		T6	244		T31	3
valid_sources[0x65]	34352	1			T4	1		T6	203		T15	2
valid_sources[0x66]	34357	1			T3	1		T6	221		T9	272
valid_sources[0x67]	35956	1			T3	1		T6	163		T12	3
valid_sources[0x68]	34183	1			T4	1		T6	248		T31	1
valid_sources[0x69]	33445	1			T6	184		T9	243		T18	4
valid_sources[0x6a]	34685	1			T6	220		T9	238		T14	1
valid_sources[0x6b]	33627	1			T3	1		T6	266		T113	1
valid_sources[0x6c]	34036	1			T3	1		T6	204		T113	1
valid_sources[0x6d]	33555	1			T6	228		T72	1		T9	221
valid_sources[0x6e]	34323	1			T3	1		T6	203		T9	225
valid_sources[0x6f]	34481	1			T6	194		T72	2		T9	239
valid_sources[0x70]	34327	1			T3	1		T6	202		T113	1
valid_sources[0x71]	33356	1			T3	2		T6	256		T72	5
valid_sources[0x72]	36112	1			T6	198		T72	6		T9	220
valid_sources[0x73]	34379	1			T6	218		T113	1		T9	231
valid_sources[0x74]	34133	1			T3	1		T6	198		T72	6
valid_sources[0x75]	33858	1			T6	248		T72	2		T42	7
valid_sources[0x76]	33199	1			T6	203		T9	242		T18	4
valid_sources[0x77]	33941	1			T3	1		T6	240		T9	260
valid_sources[0x78]	35160	1			T6	201		T9	224		T119	2
valid_sources[0x79]	34269	1			T6	215		T72	4		T15	1
valid_sources[0x7a]	35325	1			T3	3		T6	239		T9	250
valid_sources[0x7b]	33520	1			T3	3		T6	223		T15	1
valid_sources[0x7c]	34941	1			T6	221		T9	222		T119	1
valid_sources[0x7d]	32772	1			T6	188		T113	1		T9	258
valid_sources[0x7e]	34716	1			T4	1		T6	232		T9	250
valid_sources[0x7f]	34415	1			T3	2		T6	225		T31	1
valid_sources[0x80]	35440	1			T6	225		T9	236		T14	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2181264

1

T3

70

T4

20

T6

13540

values[0x0]

all_enables

biggest_size

3201946

1

T3

38

T4

9

T6

19965

values[0x1]

all_enables

biggest_size

3201434

1

T3

32

T4

11

T6

20323