Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24153137

1

T1

369

T2

821

T3

991

full_word

7900940

1

T1

177

T2

189

T3

722

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32053757	1			T1	546		T2	1010		T3	1713
auto[TlIntgErrCmd]	107	1			T288	4		T289	4		T290	9
auto[TlIntgErrData]	113	1			T288	10		T289	5		T290	4
auto[TlIntgErrBoth]	100	1			T288	6		T289	1		T290	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9278163

1

T1

326

T2

783

T3

1037

auto[1]

22775914

1

T1

220

T2

227

T3

676

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5866377	1			T1	237		T2	686		T3	586
auto[TlIntgErrNone]	partial	auto[1]	18286465	1			T1	132		T2	135		T3	405
auto[TlIntgErrNone]	full_word	auto[0]	3411661	1			T1	89		T2	97		T3	451
auto[TlIntgErrNone]	full_word	auto[1]	4489254	1			T1	88		T2	92		T3	271
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T288	2		T289	3		T290	5
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T288	1		T289	1		T290	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T288	1		T382	1		T380	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T373	2		T376	1		T382	2
auto[TlIntgErrData]	partial	auto[0]	47	1			T288	4		T290	1		T373	4
auto[TlIntgErrData]	partial	auto[1]	55	1			T288	4		T289	3		T290	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T288	2		T289	1		T290	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T289	1		T290	1		T373	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T288	2		T290	2		T373	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T288	3		T289	1		T290	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T383	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T288	1		T373	1		T375	1