Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	463159778	7722008	0	0
check_regwen_rd_A	463159778	2978	0	0
check_timeout_rd_A	463159778	1928	0	0
check_trigger_regwen_rd_A	463159778	2990	0	0
consistency_check_period_rd_A	463159778	3236	0	0
creator_sw_cfg_read_lock_rd_A	463159778	1906	0	0
direct_access_address_rd_A	463159778	1527	0	0
direct_access_wdata_0_rd_A	463159778	1044	0	0
direct_access_wdata_1_rd_A	463159778	1179	0	0
integrity_check_period_rd_A	463159778	3019	0	0
intr_enable_rd_A	463159778	3854	0	0
owner_sw_cfg_read_lock_rd_A	463159778	1678	0	0
rot_creator_auth_codesign_read_lock_rd_A	463159778	1953	0	0
rot_creator_auth_state_read_lock_rd_A	463159778	1793	0	0
vendor_test_read_lock_rd_A	463159778	1791	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	7722008	0	0
T6	160576	48423	0	0
T7	54286	0	0	0
T8	365838	0	0	0
T9	0	61413	0	0
T12	44741	0	0	0
T13	0	98529	0	0
T15	60255	0	0	0
T19	0	120855	0	0
T20	0	148207	0	0
T21	0	76406	0	0
T41	0	194370	0	0
T70	45700	0	0	0
T72	96755	0	0	0
T112	55163	0	0	0
T113	13334	0	0	0
T114	10537	0	0	0
T161	0	138699	0	0
T260	0	69109	0	0
T297	0	24699	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	2978	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	151	0	0
T117	84375	0	0	0
T141	0	74	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	41	0	0
T260	361484	89	0	0
T267	11277	0	0	0
T278	0	146	0	0
T279	0	63	0	0
T300	0	195	0	0
T332	0	71	0	0
T343	0	5	0	0
T363	0	30	0	0
T364	78244	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1928	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	235	0	0
T117	84375	0	0	0
T141	0	108	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	54	0	0
T260	361484	49	0	0
T267	11277	0	0	0
T278	0	91	0	0
T279	0	44	0	0
T300	0	234	0	0
T332	0	62	0	0
T343	0	31	0	0
T363	0	57	0	0
T364	78244	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	2990	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	195	0	0
T117	84375	0	0	0
T141	0	105	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	59	0	0
T260	361484	68	0	0
T267	11277	0	0	0
T278	0	119	0	0
T279	0	14	0	0
T300	0	257	0	0
T332	0	26	0	0
T343	0	47	0	0
T363	0	26	0	0
T364	78244	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	3236	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	161	0	0
T117	84375	0	0	0
T141	0	108	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	53	0	0
T260	361484	79	0	0
T267	11277	0	0	0
T278	0	154	0	0
T279	0	41	0	0
T300	0	212	0	0
T332	0	55	0	0
T343	0	8	0	0
T363	0	36	0	0
T364	78244	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1906	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	142	0	0
T117	84375	0	0	0
T141	0	122	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	71	0	0
T260	361484	62	0	0
T267	11277	0	0	0
T278	0	119	0	0
T279	0	62	0	0
T300	0	249	0	0
T332	0	38	0	0
T343	0	20	0	0
T363	0	59	0	0
T364	78244	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1527	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	153	0	0
T117	84375	0	0	0
T141	0	133	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	61	0	0
T260	361484	89	0	0
T267	11277	0	0	0
T278	0	112	0	0
T279	0	56	0	0
T300	0	250	0	0
T332	0	21	0	0
T343	0	45	0	0
T363	0	19	0	0
T364	78244	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1044	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	115	0	0
T117	84375	0	0	0
T141	0	66	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	20	0	0
T260	361484	62	0	0
T267	11277	0	0	0
T278	0	120	0	0
T279	0	33	0	0
T300	0	154	0	0
T332	0	4	0	0
T343	0	18	0	0
T363	0	24	0	0
T364	78244	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1179	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	66	0	0
T117	84375	0	0	0
T141	0	110	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	51	0	0
T260	361484	54	0	0
T267	11277	0	0	0
T278	0	92	0	0
T279	0	34	0	0
T300	0	270	0	0
T332	0	18	0	0
T343	0	26	0	0
T363	0	47	0	0
T364	78244	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	3019	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	170	0	0
T117	84375	0	0	0
T141	0	106	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	87	0	0
T260	361484	102	0	0
T267	11277	0	0	0
T278	0	71	0	0
T279	0	41	0	0
T300	0	167	0	0
T332	0	42	0	0
T343	0	27	0	0
T363	0	17	0	0
T364	78244	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	3854	0	0
T8	365838	10	0	0
T15	60255	0	0	0
T16	11360	0	0	0
T70	45700	0	0	0
T74	9297	0	0	0
T102	0	198	0	0
T112	55163	0	0	0
T113	13334	0	0	0
T114	10537	0	0	0
T115	12574	0	0	0
T116	10159	0	0	0
T127	0	24	0	0
T141	0	149	0	0
T256	0	67	0	0
T260	0	83	0	0
T278	0	98	0	0
T279	0	37	0	0
T300	0	265	0	0
T363	0	21	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1678	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	173	0	0
T117	84375	0	0	0
T141	0	142	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	89	0	0
T260	361484	67	0	0
T267	11277	0	0	0
T278	0	69	0	0
T279	0	41	0	0
T300	0	189	0	0
T332	0	37	0	0
T343	0	38	0	0
T363	0	15	0	0
T364	78244	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1953	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	148	0	0
T117	84375	0	0	0
T141	0	144	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	90	0	0
T260	361484	55	0	0
T267	11277	0	0	0
T278	0	132	0	0
T279	0	85	0	0
T300	0	211	0	0
T332	0	23	0	0
T343	0	27	0	0
T363	0	33	0	0
T364	78244	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1793	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	176	0	0
T117	84375	0	0	0
T141	0	98	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	66	0	0
T260	361484	39	0	0
T267	11277	0	0	0
T278	0	135	0	0
T279	0	26	0	0
T300	0	175	0	0
T332	0	55	0	0
T343	0	29	0	0
T363	0	39	0	0
T364	78244	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463159778	1791	0	0
T28	14693	0	0	0
T66	118511	0	0	0
T77	28177	0	0	0
T102	0	113	0	0
T117	84375	0	0	0
T141	0	138	0	0
T178	11337	0	0	0
T179	11432	0	0	0
T216	11701	0	0	0
T256	0	58	0	0
T260	361484	60	0	0
T267	11277	0	0	0
T278	0	83	0	0
T279	0	60	0	0
T300	0	220	0	0
T332	0	69	0	0
T343	0	46	0	0
T363	0	21	0	0
T364	78244	0	0	0