Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81,T156,T153
1	Covered	T81,T156,T153

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T72
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T119,T192
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T193,T194,T195
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T8,T112
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T16,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T6,T8,T112
CheckFailError	317	Covered	T81,T156,T153
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T112,T9
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T6,T8,T112
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T81,T156,T153
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T6,T8,T112
NoError->CheckFailError	317	Covered	T81,T156,T153
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T14,T139,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T8,T112
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T72,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T72,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81,T156,T153
1	0	Covered	T81,T156,T153
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	460186047	459343934	0	0
DigestKnown_A	460186047	459343934	0	0
DigestOffsetMustBeRepresentable_A	1146	1146	0	0
EccErrorState_A	460186047	10372	0	0
ErrorKnown_A	460186047	459343934	0	0
FsmStateKnown_A	460186047	459343934	0	0
InitDoneKnown_A	460186047	459343934	0	0
InitReadLocksPartition_A	460186047	92220274	0	0
InitWriteLocksPartition_A	460186047	92220274	0	0
OffsetMustBeBlockAligned_A	1146	1146	0	0
OtpAddrKnown_A	460186047	459343934	0	0
OtpCmdKnown_A	460186047	459343934	0	0
OtpErrorState_A	460186047	0	0	0
OtpReqKnown_A	460186047	459343934	0	0
OtpSizeKnown_A	460186047	459343934	0	0
OtpWdataKnown_A	460186047	459343934	0	0
ReadLockPropagation_A	460186047	203257251	0	0
SizeMustBeBlockAligned_A	1146	1146	0	0
TlulGntKnown_A	460186047	459343934	0	0
TlulRdataKnown_A	460186047	459343934	0	0
TlulReadOnReadLock_A	460186047	7371	0	0
TlulRerrorKnown_A	460186047	459343934	0	0
TlulRvalidKnown_A	460186047	459343934	0	0
WriteLockPropagation_A	460186047	2077900	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	460186047	27488639	0	0
u_state_regs_A	460186047	459343934	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	10372	0	0
T78	37959	0	0	0
T81	12274	3240	0	0
T128	9461	0	0	0
T141	923322	0	0	0
T153	0	3596	0	0
T156	0	3536	0	0
T168	12532	0	0	0
T169	5298	0	0	0
T170	9152	0	0	0
T171	12828	0	0	0
T172	71291	0	0	0
T173	9572	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	92220274	0	0
T1	12409	3549	0	0
T2	9535	4182	0	0
T3	27936	20229	0	0
T4	68412	417	0	0
T5	12191	4786	0	0
T6	160576	308292	0	0
T7	54286	4496	0	0
T10	14213	4742	0	0
T11	12455	4806	0	0
T12	44741	315	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	92220274	0	0
T1	12409	3549	0	0
T2	9535	4182	0	0
T3	27936	20229	0	0
T4	68412	417	0	0
T5	12191	4786	0	0
T6	160576	308292	0	0
T7	54286	4496	0	0
T10	14213	4742	0	0
T11	12455	4806	0	0
T12	44741	315	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	203257251	0	0
T3	27936	20147	0	0
T4	68412	0	0	0
T5	12191	0	0	0
T6	160576	876631	0	0
T7	54286	0	0	0
T8	365838	186797	0	0
T9	0	161039	0	0
T10	14213	0	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T31	0	1020	0	0
T42	0	5218	0	0
T70	0	1897	0	0
T72	96755	0	0	0
T112	0	45620	0	0
T113	0	5384	0	0
T118	0	456	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	7371	0	0
T3	27936	13	0	0
T4	68412	0	0	0
T5	12191	0	0	0
T6	160576	6	0	0
T7	54286	0	0	0
T8	365838	26	0	0
T9	0	24	0	0
T10	14213	0	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T16	0	3	0	0
T42	0	3	0	0
T70	0	4	0	0
T72	96755	9	0	0
T112	0	10	0	0
T113	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	2077900	0	0
T14	0	7780	0	0
T18	113518	11262	0	0
T71	98567	11848	0	0
T73	10977	0	0	0
T105	17232	0	0	0
T106	0	3148	0	0
T108	0	6394	0	0
T111	0	7106	0	0
T117	0	9526	0	0
T122	14476	0	0	0
T125	25357	0	0	0
T127	0	42288	0	0
T139	0	6392	0	0
T152	22307	0	0	0
T174	11918	0	0	0
T185	0	10173	0	0
T189	20199	0	0	0
T190	28204	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	27488639	0	0
T2	9535	3450	0	0
T3	27936	0	0	0
T4	68412	0	0	0
T5	12191	0	0	0
T6	160576	0	0	0
T7	54286	0	0	0
T8	0	81340	0	0
T10	14213	0	0	0
T11	12455	3411	0	0
T12	44741	0	0	0
T18	0	110835	0	0
T31	0	18118	0	0
T32	0	4928	0	0
T71	0	78246	0	0
T72	96755	0	0	0
T73	0	3290	0	0
T113	0	3256	0	0
T115	0	2849	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T126

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T70,T66,T67

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T80,T81,T157
1	Covered	T80,T81,T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T72
1	1	Covered	T1,T2,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T72,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T72,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T5
ReadWaitSt	252	Covered	T1,T2,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T5
InitSt->ErrorSt	315	Covered	T119,T193,T194
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T11,T114,T115
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T8,T112
ReadSt->ReadWaitSt	252	Covered	T1,T2,T5
ReadWaitSt->ErrorSt	276	Covered	T72,T32,T182
ReadWaitSt->IdleSt	270	Covered	T1,T2,T5
ResetSt->ErrorSt	315	Covered	T16,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T6,T8,T112
CheckFailError	317	Covered	T80,T81,T157
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T1,T5,T70
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T112,T9
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T8,T112
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T80,T81,T157
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T5,T126
MacroEccCorrError->NoError	235	Covered	T70,T66,T67
NoError->AccessError	256	Covered	T6,T8,T112
NoError->CheckFailError	317	Covered	T80,T81,T157
NoError->FsmStateError	289	Covered	T2,T3,T10
NoError->MacroEccCorrError	221	Covered	T1,T5,T70

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T72,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T126
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T11,T114,T115
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T14,T139
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T8,T112
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T70,T66,T67
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T72,T32,T182
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T72,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T72,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T80,T81,T157
1	0	Covered	T80,T81,T157
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	460186047	459343934	0	0
DigestKnown_A	460186047	459343934	0	0
DigestOffsetMustBeRepresentable_A	1146	1146	0	0
EccErrorState_A	460186047	20049	0	0
ErrorKnown_A	460186047	459343934	0	0
FsmStateKnown_A	460186047	459343934	0	0
InitDoneKnown_A	460186047	459343934	0	0
InitReadLocksPartition_A	460186047	92398442	0	0
InitWriteLocksPartition_A	460186047	92398442	0	0
OffsetMustBeBlockAligned_A	1146	1146	0	0
OtpAddrKnown_A	460186047	459343934	0	0
OtpCmdKnown_A	460186047	459343934	0	0
OtpErrorState_A	460186047	62	0	0
OtpReqKnown_A	460186047	459343934	0	0
OtpSizeKnown_A	460186047	459343934	0	0
OtpWdataKnown_A	460186047	459343934	0	0
ReadLockPropagation_A	460186047	209837722	0	0
SizeMustBeBlockAligned_A	1146	1146	0	0
TlulGntKnown_A	460186047	459343934	0	0
TlulRdataKnown_A	460186047	459343934	0	0
TlulReadOnReadLock_A	460186047	7611	0	0
TlulRerrorKnown_A	460186047	459343934	0	0
TlulRvalidKnown_A	460186047	459343934	0	0
WriteLockPropagation_A	460186047	2464938	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	460186047	28201163	0	0
u_state_regs_A	460186047	459343934	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	20049	0	0
T22	286454	0	0	0
T80	15626	2729	0	0
T81	0	3240	0	0
T153	0	3596	0	0
T154	0	3525	0	0
T157	0	3997	0	0
T159	0	2962	0	0
T160	36673	0	0	0
T161	586268	0	0	0
T162	224717	0	0	0
T163	52941	0	0	0
T164	15111	0	0	0
T165	10570	0	0	0
T166	563743	0	0	0
T167	10671	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	92398442	0	0
T1	12409	3583	0	0
T2	9535	4216	0	0
T3	27936	20297	0	0
T4	68412	519	0	0
T5	12191	4837	0	0
T6	160576	308394	0	0
T7	54286	4615	0	0
T10	14213	4776	0	0
T11	12455	4830	0	0
T12	44741	417	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	92398442	0	0
T1	12409	3583	0	0
T2	9535	4216	0	0
T3	27936	20297	0	0
T4	68412	519	0	0
T5	12191	4837	0	0
T6	160576	308394	0	0
T7	54286	4615	0	0
T10	14213	4776	0	0
T11	12455	4830	0	0
T12	44741	417	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	62	0	0
T6	160576	0	0	0
T7	54286	0	0	0
T8	365838	0	0	0
T11	12455	1	0	0
T12	44741	0	0	0
T15	60255	0	0	0
T32	0	1	0	0
T70	45700	0	0	0
T72	96755	1	0	0
T112	55163	0	0	0
T113	13334	0	0	0
T114	0	1	0	0
T115	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	209837722	0	0
T3	27936	20107	0	0
T4	68412	0	0	0
T5	12191	0	0	0
T6	160576	544056	0	0
T7	54286	0	0	0
T8	365838	206493	0	0
T9	0	245682	0	0
T10	14213	0	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T31	0	2809	0	0
T42	0	4886	0	0
T70	0	2591	0	0
T72	96755	0	0	0
T112	0	45608	0	0
T113	0	5384	0	0
T118	0	454	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	7611	0	0
T3	27936	15	0	0
T4	68412	0	0	0
T5	12191	0	0	0
T6	160576	10	0	0
T7	54286	0	0	0
T8	365838	28	0	0
T9	0	38	0	0
T10	14213	0	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T16	0	3	0	0
T42	0	2	0	0
T70	0	5	0	0
T72	96755	7	0	0
T112	0	13	0	0
T113	0	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	2464938	0	0
T9	302393	0	0	0
T14	0	10446	0	0
T18	113518	11262	0	0
T31	48602	0	0	0
T32	84440	0	0	0
T42	23000	2651	0	0
T57	15093	0	0	0
T66	0	20393	0	0
T71	98567	0	0	0
T73	10977	0	0	0
T106	0	3148	0	0
T107	0	6035	0	0
T108	0	6867	0	0
T110	0	6669	0	0
T118	8878	0	0	0
T119	24433	0	0	0
T127	0	19448	0	0
T139	0	3524	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	28201163	0	0
T6	160576	0	0	0
T7	54286	0	0	0
T8	365838	52913	0	0
T11	12455	3406	0	0
T12	44741	0	0	0
T15	60255	0	0	0
T18	0	975586	0	0
T31	0	18033	0	0
T32	0	4911	0	0
T42	0	15109	0	0
T70	45700	0	0	0
T71	0	63508	0	0
T72	96755	30830	0	0
T112	55163	0	0	0
T113	13334	0	0	0
T114	0	3455	0	0
T115	0	2844	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T116,T83

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T72,T70,T66

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T153,T154,T155
1	Covered	T153,T154,T155

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T72
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T72,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T72,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T119,T193,T194
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T5,T10,T11
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T8,T112
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T72,T162,T196
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T16,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T6,T8,T112
CheckFailError	317	Covered	T153,T154,T155
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T2,T72,T70
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T112,T9
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T8,T112
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T153,T154,T155
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T2,T72,T116
MacroEccCorrError->NoError	235	Covered	T70,T66,T67
NoError->AccessError	256	Covered	T6,T8,T112
NoError->CheckFailError	317	Covered	T153,T154,T155
NoError->FsmStateError	289	Covered	T1,T3,T11
NoError->MacroEccCorrError	221	Covered	T2,T72,T70

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T72,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T116,T83
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T174
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T139,T187,T197
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T8,T112
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T72,T70,T66
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T72,T162,T196
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T72,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T72,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T153,T154,T155
1	0	Covered	T153,T154,T155
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	460186047	459343934	0	0
DigestKnown_A	460186047	459343934	0	0
DigestOffsetMustBeRepresentable_A	1146	1146	0	0
EccErrorState_A	460186047	10831	0	0
ErrorKnown_A	460186047	459343934	0	0
FsmStateKnown_A	460186047	459343934	0	0
InitDoneKnown_A	460186047	459343934	0	0
InitReadLocksPartition_A	460186047	92575380	0	0
InitWriteLocksPartition_A	460186047	92575380	0	0
OffsetMustBeBlockAligned_A	1146	1146	0	0
OtpAddrKnown_A	460186047	459343934	0	0
OtpCmdKnown_A	460186047	459343934	0	0
OtpErrorState_A	460186047	51	0	0
OtpReqKnown_A	460186047	459343934	0	0
OtpSizeKnown_A	460186047	459343934	0	0
OtpWdataKnown_A	460186047	459343934	0	0
ReadLockPropagation_A	460186047	211279790	0	0
SizeMustBeBlockAligned_A	1146	1146	0	0
TlulGntKnown_A	460186047	459343934	0	0
TlulRdataKnown_A	460186047	459343934	0	0
TlulReadOnReadLock_A	460186047	7821	0	0
TlulRerrorKnown_A	460186047	459343934	0	0
TlulRvalidKnown_A	460186047	459343934	0	0
WriteLockPropagation_A	460186047	1756708	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	460186047	17087142	0	0
u_state_regs_A	460186047	459343934	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	10831	0	0
T153	16313	3596	0	0
T154	0	3525	0	0
T155	0	3710	0	0
T198	23202	0	0	0
T199	18780	0	0	0
T200	16435	0	0	0
T201	11067	0	0	0
T202	70094	0	0	0
T203	13363	0	0	0
T204	112346	0	0	0
T205	594283	0	0	0
T206	10462	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	92575380	0	0
T1	12409	3617	0	0
T2	9535	4250	0	0
T3	27936	20365	0	0
T4	68412	621	0	0
T5	12191	4878	0	0
T6	160576	308496	0	0
T7	54286	4734	0	0
T10	14213	4800	0	0
T11	12455	4847	0	0
T12	44741	519	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	92575380	0	0
T1	12409	3617	0	0
T2	9535	4250	0	0
T3	27936	20365	0	0
T4	68412	621	0	0
T5	12191	4878	0	0
T6	160576	308496	0	0
T7	54286	4734	0	0
T10	14213	4800	0	0
T11	12455	4847	0	0
T12	44741	519	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	51	0	0
T5	12191	1	0	0
T6	160576	0	0	0
T7	54286	0	0	0
T8	365838	0	0	0
T10	14213	1	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T15	60255	0	0	0
T72	96755	1	0	0
T112	55163	0	0	0
T162	0	1	0	0
T167	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T179	0	1	0	0
T181	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	211279790	0	0
T3	27936	20095	0	0
T4	68412	0	0	0
T5	12191	0	0	0
T6	160576	877610	0	0
T7	54286	0	0	0
T8	365838	111971	0	0
T9	0	244161	0	0
T10	14213	0	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T31	0	1548	0	0
T42	0	5752	0	0
T70	0	2555	0	0
T72	96755	0	0	0
T112	0	45434	0	0
T113	0	5122	0	0
T118	0	452	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1146	1146	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	7821	0	0
T3	27936	21	0	0
T4	68412	0	0	0
T5	12191	0	0	0
T6	160576	9	0	0
T7	54286	0	0	0
T8	365838	24	0	0
T9	0	40	0	0
T10	14213	0	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T16	0	3	0	0
T42	0	3	0	0
T70	0	4	0	0
T72	96755	12	0	0
T112	0	7	0	0
T113	0	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	1756708	0	0
T14	357903	4348	0	0
T106	53331	0	0	0
T107	93094	0	0	0
T109	0	4963	0	0
T130	71984	0	0	0
T131	0	3673	0	0
T134	0	4492	0	0
T139	80662	2311	0	0
T175	10360	0	0	0
T184	0	2346	0	0
T185	0	4577	0	0
T186	0	5228	0	0
T187	0	17790	0	0
T188	0	9197	0	0
T191	62877	0	0	0
T207	8327	0	0	0
T208	12979	0	0	0
T209	28775	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	17087142	0	0
T6	160576	0	0	0
T7	54286	0	0	0
T8	365838	47253	0	0
T10	14213	4026	0	0
T11	12455	0	0	0
T12	44741	0	0	0
T14	0	57866	0	0
T15	60255	0	0	0
T32	0	4894	0	0
T42	0	15058	0	0
T70	45700	0	0	0
T72	96755	30711	0	0
T112	55163	0	0	0
T130	0	54469	0	0
T139	0	66931	0	0
T152	0	12284	0	0
T175	0	3756	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460186047	459343934	0	0
T1	12409	12141	0	0
T2	9535	9269	0	0
T3	27936	27661	0	0
T4	68412	68049	0	0
T5	12191	11908	0	0
T6	160576	160563	0	0
T7	54286	53865	0	0
T10	14213	13930	0	0
T11	12455	12238	0	0
T12	44741	44349	0	0