Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

27817664

1

T1

3605

T2

3284

T3

11

full_word

9002232

1

T1

3089

T2

2610

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36819556	1			T1	6694		T2	5894		T3	15
auto[TlIntgErrCmd]	117	1			T269	7		T270	5		T271	1
auto[TlIntgErrData]	106	1			T269	6		T270	8		T271	4
auto[TlIntgErrBoth]	117	1			T269	7		T270	7		T271	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10456468

1

T1

6102

T2

5274

T3

1

auto[1]

26363428

1

T1

592

T2

620

T3

14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6662304	1			T1	3251		T2	2912		T3	1
auto[TlIntgErrNone]	partial	auto[1]	21155047	1			T1	354		T2	372		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	3794012	1			T1	2851		T2	2362		T4	218
auto[TlIntgErrNone]	full_word	auto[1]	5208193	1			T1	238		T2	248		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T269	3		T270	2		T339	3
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T269	3		T270	3		T271	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T339	1		T346	1		T343	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T269	1		T340	2		T345	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T269	3		T270	2		T339	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T269	3		T270	5		T271	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T271	1		T347	1		T343	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T270	1		T275	1		T348	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T269	2		T270	5		T339	4
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T269	4		T270	2		T271	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T339	1		T340	1		T341	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T269	1		T346	1		T349	1