Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22	98.61	85.95			92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram	98.64	100.00	94.55			100.00	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.64	100.00	94.55			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.04	89.75	92.65			89.77	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	100.00	100.00	100.00			100.00	100.00
u_reqfifo	91.36	95.00	87.10			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	92.37	95.00	89.47			85.00	100.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	91.36	95.00	87.10			83.33	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		72	71	98.61
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	8	7	87.50
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
ALWAYS	521	3	3	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132		unreachable
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	0	1
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
452	1	1
453	1	1
454	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477	1	1
479	1	1
481	1	1
490	1	1
521	1	1
522	1	1
523	1	1
527	1	1
530	1	1
535	1	1
540	1	1

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	121	104	85.95
Logical	121	104	85.95
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T12,T25
1	0	Covered	T1,T2,T4

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Covered	T6,T7,T8
1	0	0	0	0	0	Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T4

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T4

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T4

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T6,T7,T8
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T4

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T6,T7,T8

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T7,T8

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T8,T63,T33
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T4

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T2,T4

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T7,T8

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T7,T8

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T7,T8

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T4

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T4

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	144	2	2	100.00
TERNARY	343	2	2	100.00
TERNARY	349	3	2	66.67
TERNARY	395	2	2	100.00
TERNARY	535	2	2	100.00
IF	129	2	2	100.00
IF	283	4	3	75.00
IF	303	3	3	100.00
IF	364	2	2	100.00
IF	428	2	2	100.00
IF	440	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	349	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	535	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if (reqfifo_rvalid)
-2-:	284	if (reqfifo_rdata.error)
-3-:	287	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T6,T7,T8
1	0	1	Covered	T1,T2,T4
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if (reqfifo_rvalid)
-2-:	304	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T6,T7,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	364	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	428	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	499706234	498828298	0	0
DataIntgOptions_A	1152	1152	0	0
ReqOutKnown_A	499706234	498828298	0	0
SramDwHasByteGranularity_A	1152	1152	0	0
SramDwIsMultipleOfTlulWidth_A	1152	1152	0	0
TlOutKnownIfFifoKnown_A	499706234	498828298	0	0
TlOutValidKnown_A	499706234	498828298	0	0
WdataOutKnown_A	499706234	498828298	0	0
WeOutKnown_A	499706234	498828298	0	0
WmaskOutKnown_A	499706234	498828298	0	0
adapterNoReadOrWrite	1152	1152	0	0
rvalidHighReqFifoEmpty	499706234	108495	0	0
rvalidHighWhenRspFifoFull	499706234	108495	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	108495	0	0
T1	53334	61	0	0
T2	305640	55	0	0
T3	4303	0	0	0
T4	46598	16	0	0
T5	29520	28	0	0
T6	0	440	0	0
T9	10744	13	0	0
T10	9092	0	0	0
T11	12982	17	0	0
T12	184453	39	0	0
T13	32648	24	0	0
T25	0	42	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	108495	0	0
T1	53334	61	0	0
T2	305640	55	0	0
T3	4303	0	0	0
T4	46598	16	0	0
T5	29520	28	0	0
T6	0	440	0	0
T9	10744	13	0	0
T10	9092	0	0	0
T11	12982	17	0	0
T12	184453	39	0	0
T13	32648	24	0	0
T25	0	42	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
ALWAYS	281	7	7	100.00
ALWAYS	301	6	6	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	3	3	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
ALWAYS	425	6	6	100.00
ALWAYS	437	5	5	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
ALWAYS	521	3	3	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132		unreachable
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
274	1	1
275	1	1
276	1	1
281	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291		excluded
			Exclude Annotation: VC_COV_UNR
294	1	1
301	1	1
303	1	1
304	1	1
305	1	1
307	1	1
310	1	1
315	1	1
319	1	1
338	1	1
343	1	1
349	1	1
361	1	1
364	1	1
365	1	1
367	1	1
371	1	1
392	1	1
393	1	1
394	1	1
395	1	1
425	1	1
426	1	1
428	1	1
429	1	1
430	1	1
431	1	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
452	1	1
453	1	1
454	1	1
458	1	1
459	1	1
461	1	1
462	1	1
469	1	1
472	1	1
476	1	1
477	1	1
479	1	1
481	1	1
490	1	1
521	1	1
522	1	1
523	1	1
527	1	1
530	1	1
535	1	1
540	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Total	Covered	Percent
Conditions	110	104	94.55
Logical	110	104	94.55
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T12,T25
1	0	Covered	T1,T2,T4

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
0	0	0	0	0	0	Covered	T1,T2,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Covered	T6,T7,T8
1	0	0	0	0	0	Excluded		VC_COV_UNR

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T4

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T4

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T4

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Covered	T6,T7,T8
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T4

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4
1	1	Excluded		VC_COV_UNR

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T6,T7,T8

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T7,T8

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T8,T63,T33
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T4

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T2,T4

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T7,T8

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T7,T8

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T7,T8

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T4

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T2,T4,T5
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T4

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	144	2	2	100.00
TERNARY	343	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	535	2	2	100.00
IF	129	2	2	100.00
IF	283	3	3	100.00
IF	303	3	3	100.00
IF	364	2	2	100.00
IF	428	2	2	100.00
IF	440	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	349	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Excluded		VC_COV_UNR
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	535	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if (reqfifo_rvalid)
-2-:	284	if (reqfifo_rdata.error)
-3-:	287	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	1	-	Covered	T6,T7,T8
1	0	1	Covered	T1,T2,T4
1	0	0	Excluded		VC_COV_UNR
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if (reqfifo_rvalid)
-2-:	304	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T6,T7,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	364	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	428	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	499706234	498828298	0	0
DataIntgOptions_A	1152	1152	0	0
ReqOutKnown_A	499706234	498828298	0	0
SramDwHasByteGranularity_A	1152	1152	0	0
SramDwIsMultipleOfTlulWidth_A	1152	1152	0	0
TlOutKnownIfFifoKnown_A	499706234	498828298	0	0
TlOutValidKnown_A	499706234	498828298	0	0
WdataOutKnown_A	499706234	498828298	0	0
WeOutKnown_A	499706234	498828298	0	0
WmaskOutKnown_A	499706234	498828298	0	0
adapterNoReadOrWrite	1152	1152	0	0
rvalidHighReqFifoEmpty	499706234	108495	0	0
rvalidHighWhenRspFifoFull	499706234	108495	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	498828298	0	0
T1	53334	53125	0	0
T2	305640	305034	0	0
T3	4303	4246	0	0
T4	46598	45768	0	0
T5	29520	29002	0	0
T9	10744	10489	0	0
T10	9092	8884	0	0
T11	12982	12705	0	0
T12	184453	183296	0	0
T13	32648	32089	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152	1152	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	108495	0	0
T1	53334	61	0	0
T2	305640	55	0	0
T3	4303	0	0	0
T4	46598	16	0	0
T5	29520	28	0	0
T6	0	440	0	0
T9	10744	13	0	0
T10	9092	0	0	0
T11	12982	17	0	0
T12	184453	39	0	0
T13	32648	24	0	0
T25	0	42	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	499706234	108495	0	0
T1	53334	61	0	0
T2	305640	55	0	0
T3	4303	0	0	0
T4	46598	16	0	0
T5	29520	28	0	0
T6	0	440	0	0
T9	10744	13	0	0
T10	9092	0	0	0
T11	12982	17	0	0
T12	184453	39	0	0
T13	32648	24	0	0
T25	0	42	0	0