Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	502898277	8985209	0	0
check_regwen_rd_A	502898277	3144	0	0
check_timeout_rd_A	502898277	2483	0	0
check_trigger_regwen_rd_A	502898277	2835	0	0
consistency_check_period_rd_A	502898277	3080	0	0
creator_sw_cfg_read_lock_rd_A	502898277	2635	0	0
direct_access_address_rd_A	502898277	2230	0	0
direct_access_wdata_0_rd_A	502898277	1288	0	0
direct_access_wdata_1_rd_A	502898277	1561	0	0
integrity_check_period_rd_A	502898277	3033	0	0
intr_enable_rd_A	502898277	3481	0	0
owner_sw_cfg_read_lock_rd_A	502898277	2298	0	0
rot_creator_auth_codesign_read_lock_rd_A	502898277	2483	0	0
rot_creator_auth_state_read_lock_rd_A	502898277	2264	0	0
vendor_test_read_lock_rd_A	502898277	2252	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	8985209	0	0
T6	197344	32515	0	0
T7	422700	124264	0	0
T8	391761	78758	0	0
T14	0	49977	0	0
T16	0	159745	0	0
T33	0	156531	0	0
T50	12597	0	0	0
T63	0	25847	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T105	14401	0	0	0
T106	9149	0	0	0
T107	63589	0	0	0
T108	20805	0	0	0
T131	0	57359	0	0
T134	0	235758	0	0
T142	0	227464	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	3144	0	0
T8	391761	137	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	198	0	0
T63	0	41	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	82	0	0
T179	0	55	0	0
T182	0	66	0	0
T185	0	204	0	0
T202	15181	0	0	0
T258	0	34	0	0
T321	0	89	0	0
T326	0	170	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2483	0	0
T8	391761	72	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	234	0	0
T63	0	40	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	60	0	0
T179	0	38	0	0
T182	0	54	0	0
T185	0	176	0	0
T202	15181	0	0	0
T258	0	45	0	0
T321	0	142	0	0
T326	0	255	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2835	0	0
T8	391761	91	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	156	0	0
T63	0	40	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	71	0	0
T179	0	74	0	0
T182	0	62	0	0
T185	0	203	0	0
T202	15181	0	0	0
T258	0	56	0	0
T321	0	133	0	0
T326	0	227	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	3080	0	0
T8	391761	111	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	178	0	0
T63	0	59	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	58	0	0
T179	0	35	0	0
T182	0	75	0	0
T185	0	205	0	0
T202	15181	0	0	0
T258	0	46	0	0
T321	0	152	0	0
T326	0	162	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2635	0	0
T8	391761	87	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	181	0	0
T63	0	69	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	91	0	0
T179	0	44	0	0
T182	0	58	0	0
T185	0	200	0	0
T202	15181	0	0	0
T258	0	58	0	0
T321	0	168	0	0
T326	0	210	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2230	0	0
T8	391761	82	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	190	0	0
T63	0	43	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	57	0	0
T179	0	64	0	0
T182	0	63	0	0
T185	0	144	0	0
T202	15181	0	0	0
T258	0	66	0	0
T321	0	168	0	0
T326	0	213	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	1288	0	0
T8	391761	29	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	116	0	0
T63	0	25	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	5	0	0
T179	0	18	0	0
T182	0	21	0	0
T185	0	131	0	0
T202	15181	0	0	0
T258	0	45	0	0
T321	0	72	0	0
T326	0	210	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	1561	0	0
T8	391761	107	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	139	0	0
T63	0	31	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	63	0	0
T179	0	19	0	0
T182	0	38	0	0
T185	0	127	0	0
T202	15181	0	0	0
T258	0	16	0	0
T321	0	104	0	0
T326	0	165	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	3033	0	0
T8	391761	96	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	213	0	0
T63	0	44	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	61	0	0
T179	0	78	0	0
T182	0	63	0	0
T185	0	124	0	0
T202	15181	0	0	0
T258	0	36	0	0
T321	0	147	0	0
T326	0	194	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	3481	0	0
T8	391761	45	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	167	0	0
T34	0	27	0	0
T63	0	48	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T123	0	21	0	0
T179	0	53	0	0
T182	0	50	0	0
T185	0	163	0	0
T202	15181	0	0	0
T258	0	60	0	0
T326	0	196	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2298	0	0
T8	391761	81	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	211	0	0
T63	0	38	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	27	0	0
T179	0	32	0	0
T182	0	56	0	0
T185	0	148	0	0
T202	15181	0	0	0
T258	0	51	0	0
T321	0	154	0	0
T326	0	139	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2483	0	0
T8	391761	69	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	139	0	0
T63	0	34	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	41	0	0
T179	0	64	0	0
T182	0	71	0	0
T185	0	183	0	0
T202	15181	0	0	0
T258	0	98	0	0
T321	0	161	0	0
T326	0	200	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2264	0	0
T8	391761	56	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	144	0	0
T63	0	31	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	93	0	0
T179	0	49	0	0
T182	0	105	0	0
T185	0	134	0	0
T202	15181	0	0	0
T258	0	52	0	0
T321	0	111	0	0
T326	0	144	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502898277	2252	0	0
T8	391761	95	0	0
T16	889113	0	0	0
T19	104126	0	0	0
T29	16740	0	0	0
T33	0	183	0	0
T63	0	29	0	0
T64	17190	0	0	0
T65	10657	0	0	0
T108	20805	0	0	0
T109	19563	0	0	0
T110	37147	0	0	0
T120	0	68	0	0
T179	0	42	0	0
T182	0	52	0	0
T185	0	134	0	0
T202	15181	0	0	0
T258	0	69	0	0
T321	0	113	0	0
T326	0	139	0	0