Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7284040	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7187690

1

T1

440

T2

164

T3

2782

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8379918	1			T1	2172		T2	348		T3	5352
values[0x0]	2322009	1			T1	72		T2	97		T3	285
values[0x1]	3769803	1			T1	67		T2	104		T3	259

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4718829	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9752901

1

T1

1011

T2

271

T3

3424

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	59091	1			T5	399		T6	241		T9	58
valid_sources[0x01]	65568	1			T4	1		T5	398		T6	262
valid_sources[0x02]	48907	1			T4	3		T5	401		T6	252
valid_sources[0x03]	50240	1			T5	395		T6	242		T9	21
valid_sources[0x04]	51428	1			T4	2		T5	400		T6	256
valid_sources[0x05]	48010	1			T5	393		T6	273		T9	37
valid_sources[0x06]	63495	1			T4	2		T5	397		T6	277
valid_sources[0x07]	49587	1			T5	405		T6	296		T9	32
valid_sources[0x08]	50931	1			T5	366		T6	262		T9	66
valid_sources[0x09]	50168	1			T5	377		T6	252		T9	39
valid_sources[0x0a]	69181	1			T5	443		T6	240		T9	70
valid_sources[0x0b]	47628	1			T4	5		T5	384		T6	201
valid_sources[0x0c]	56985	1			T3	5896		T4	4		T5	378
valid_sources[0x0d]	49366	1			T5	425		T6	279		T9	63
valid_sources[0x0e]	51272	1			T4	4		T5	411		T6	274
valid_sources[0x0f]	54469	1			T4	4		T5	436		T6	327
valid_sources[0x10]	51781	1			T4	13		T5	411		T6	290
valid_sources[0x11]	52610	1			T4	3		T5	368		T6	275
valid_sources[0x12]	49116	1			T4	2		T5	442		T6	236
valid_sources[0x13]	52830	1			T4	1		T5	392		T6	272
valid_sources[0x14]	51879	1			T5	404		T6	328		T9	39
valid_sources[0x15]	49780	1			T4	6		T5	400		T6	205
valid_sources[0x16]	48535	1			T5	407		T6	245		T9	37
valid_sources[0x17]	53507	1			T5	383		T6	223		T9	57
valid_sources[0x18]	59367	1			T4	7		T5	409		T6	325
valid_sources[0x19]	86429	1			T5	415		T6	285		T9	67
valid_sources[0x1a]	54894	1			T4	1		T5	393		T6	314
valid_sources[0x1b]	56851	1			T4	4		T5	394		T6	280
valid_sources[0x1c]	49419	1			T4	1		T5	365		T6	239
valid_sources[0x1d]	54961	1			T4	8		T5	412		T6	311
valid_sources[0x1e]	49057	1			T4	5		T5	406		T6	255
valid_sources[0x1f]	53187	1			T4	1		T5	390		T6	278
valid_sources[0x20]	60734	1			T4	10		T5	414		T6	222
valid_sources[0x21]	61870	1			T4	2		T5	381		T6	265
valid_sources[0x22]	51566	1			T4	5		T5	376		T6	297
valid_sources[0x23]	52113	1			T5	358		T6	256		T9	70
valid_sources[0x24]	64018	1			T5	390		T6	339		T9	42
valid_sources[0x25]	51259	1			T5	391		T6	304		T9	34
valid_sources[0x26]	85099	1			T4	3		T5	397		T6	256
valid_sources[0x27]	57700	1			T4	1		T5	414		T6	245
valid_sources[0x28]	48767	1			T4	9		T5	367		T6	309
valid_sources[0x29]	47936	1			T5	384		T6	276		T9	62
valid_sources[0x2a]	48759	1			T4	3		T5	391		T6	229
valid_sources[0x2b]	49808	1			T4	2		T5	418		T6	257
valid_sources[0x2c]	68268	1			T4	4		T5	400		T6	265
valid_sources[0x2d]	52645	1			T4	3		T5	377		T6	303
valid_sources[0x2e]	126584	1			T5	362		T6	287		T9	32
valid_sources[0x2f]	50461	1			T4	2		T5	361		T6	288
valid_sources[0x30]	52569	1			T4	1		T5	438		T6	262
valid_sources[0x31]	62801	1			T4	3		T5	366		T6	214
valid_sources[0x32]	53573	1			T4	3		T5	395		T6	218
valid_sources[0x33]	51575	1			T4	6		T5	441		T6	258
valid_sources[0x34]	53293	1			T4	18		T5	390		T8	1306
valid_sources[0x35]	65099	1			T4	3		T5	417		T6	238
valid_sources[0x36]	50314	1			T5	363		T6	260		T9	53
valid_sources[0x37]	50457	1			T4	1		T5	377		T6	276
valid_sources[0x38]	61785	1			T5	431		T6	288		T9	69
valid_sources[0x39]	53250	1			T5	370		T6	262		T9	44
valid_sources[0x3a]	51457	1			T5	430		T6	231		T9	58
valid_sources[0x3b]	53370	1			T4	12		T5	420		T6	245
valid_sources[0x3c]	50857	1			T4	1		T5	391		T6	257
valid_sources[0x3d]	65068	1			T5	429		T6	253		T9	73
valid_sources[0x3e]	49477	1			T4	2		T5	373		T6	244
valid_sources[0x3f]	49285	1			T4	2		T5	405		T6	295
valid_sources[0x40]	51224	1			T5	386		T6	297		T9	43
valid_sources[0x41]	52968	1			T4	1		T5	382		T6	275
valid_sources[0x42]	49850	1			T5	365		T6	258		T9	33
valid_sources[0x43]	61178	1			T5	409		T6	256		T9	86
valid_sources[0x44]	59944	1			T4	1		T5	429		T6	227
valid_sources[0x45]	60014	1			T4	3		T5	405		T6	277
valid_sources[0x46]	53914	1			T4	7		T5	383		T6	255
valid_sources[0x47]	51741	1			T5	427		T6	274		T9	33
valid_sources[0x48]	50506	1			T5	443		T6	269		T9	47
valid_sources[0x49]	55073	1			T4	2		T5	389		T6	282
valid_sources[0x4a]	50805	1			T5	422		T6	275		T9	24
valid_sources[0x4b]	59966	1			T5	429		T6	292		T9	58
valid_sources[0x4c]	49423	1			T4	5		T5	413		T6	221
valid_sources[0x4d]	50244	1			T4	4		T5	453		T6	260
valid_sources[0x4e]	48015	1			T5	407		T6	304		T9	71
valid_sources[0x4f]	79886	1			T4	2		T5	419		T6	292
valid_sources[0x50]	55214	1			T4	1		T5	426		T6	288
valid_sources[0x51]	56131	1			T4	9		T5	425		T6	256
valid_sources[0x52]	49343	1			T5	340		T6	251		T9	72
valid_sources[0x53]	48809	1			T5	398		T6	291		T9	31
valid_sources[0x54]	60281	1			T4	1		T5	418		T6	310
valid_sources[0x55]	52988	1			T4	2		T5	423		T6	260
valid_sources[0x56]	51638	1			T4	5		T5	395		T6	249
valid_sources[0x57]	51614	1			T4	2		T5	389		T6	249
valid_sources[0x58]	49804	1			T5	344		T6	308		T9	75
valid_sources[0x59]	51816	1			T5	407		T6	260		T9	57
valid_sources[0x5a]	67417	1			T5	427		T6	280		T9	77
valid_sources[0x5b]	48163	1			T4	2		T5	374		T6	304
valid_sources[0x5c]	49342	1			T5	412		T6	309		T9	62
valid_sources[0x5d]	55290	1			T4	10		T5	408		T6	334
valid_sources[0x5e]	50746	1			T4	3		T5	390		T6	284
valid_sources[0x5f]	52092	1			T4	4		T5	389		T6	269
valid_sources[0x60]	48248	1			T4	7		T5	388		T6	220
valid_sources[0x61]	53645	1			T4	1		T5	417		T6	216
valid_sources[0x62]	48928	1			T5	404		T6	254		T9	26
valid_sources[0x63]	49294	1			T4	8		T5	375		T6	254
valid_sources[0x64]	53238	1			T5	374		T6	249		T9	38
valid_sources[0x65]	59939	1			T5	408		T6	223		T9	48
valid_sources[0x66]	48445	1			T4	2		T5	364		T6	313
valid_sources[0x67]	55849	1			T5	371		T6	273		T9	37
valid_sources[0x68]	55839	1			T4	1		T5	399		T6	258
valid_sources[0x69]	47592	1			T5	396		T6	275		T9	43
valid_sources[0x6a]	64113	1			T4	5		T5	404		T6	293
valid_sources[0x6b]	51188	1			T4	4		T5	430		T6	302
valid_sources[0x6c]	50432	1			T4	7		T5	395		T6	275
valid_sources[0x6d]	52043	1			T4	4		T5	385		T6	244
valid_sources[0x6e]	53755	1			T5	400		T6	231		T9	41
valid_sources[0x6f]	77234	1			T4	2		T5	406		T6	277
valid_sources[0x70]	53607	1			T5	415		T6	277		T9	68
valid_sources[0x71]	53524	1			T4	2		T5	437		T6	295
valid_sources[0x72]	50328	1			T5	379		T6	238		T9	27
valid_sources[0x73]	51985	1			T5	372		T6	269		T9	74
valid_sources[0x74]	51259	1			T5	412		T6	253		T9	42
valid_sources[0x75]	54025	1			T4	4		T5	390		T6	246
valid_sources[0x76]	49113	1			T4	1		T5	401		T6	251
valid_sources[0x77]	51174	1			T4	2		T5	388		T6	281
valid_sources[0x78]	55161	1			T4	3		T5	394		T6	202
valid_sources[0x79]	66378	1			T5	357		T6	294		T9	54
valid_sources[0x7a]	51192	1			T5	398		T6	306		T9	70
valid_sources[0x7b]	47950	1			T4	7		T5	423		T6	176
valid_sources[0x7c]	53926	1			T4	3		T5	402		T6	303
valid_sources[0x7d]	46892	1			T5	399		T6	238		T9	51
valid_sources[0x7e]	48090	1			T4	3		T5	400		T6	300
valid_sources[0x7f]	57038	1			T4	1		T5	376		T6	309
valid_sources[0x80]	67137	1			T4	1		T5	417		T6	256

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3416168

1

T1

377

T2

79

T3

2565

values[0x0]

all_enables

biggest_size

1925582

1

T1

40

T2

45

T3

131

values[0x1]

all_enables

biggest_size

1845940

1

T1

23

T2

40

T3

86

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	249874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8989006

1

T1

20

T3

180

T4

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2297760	1			T1	10		T3	90		T4	10
values[0x0]	3369268	1			T1	4		T3	42		T4	5
values[0x1]	3571852	1			T1	6		T3	48		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90386	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9148494

1

T1

20

T3

180

T4

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35931	1			T5	311		T6	1		T7	1
valid_sources[0x01]	36799	1			T5	331		T6	7		T180	1
valid_sources[0x02]	38444	1			T5	314		T6	1		T7	1
valid_sources[0x03]	35860	1			T5	331		T6	4		T7	3
valid_sources[0x04]	33930	1			T5	303		T6	5		T7	4
valid_sources[0x05]	37208	1			T5	328		T8	2		T6	2
valid_sources[0x06]	37314	1			T5	316		T6	1		T7	3
valid_sources[0x07]	35893	1			T5	313		T6	2		T180	2
valid_sources[0x08]	36537	1			T5	324		T7	3		T104	1
valid_sources[0x09]	35042	1			T5	316		T6	5		T7	3
valid_sources[0x0a]	34150	1			T5	312		T6	5		T7	3
valid_sources[0x0b]	38969	1			T5	333		T6	11		T7	1
valid_sources[0x0c]	33814	1			T4	1		T5	317		T6	5
valid_sources[0x0d]	33089	1			T5	296		T6	3		T7	6
valid_sources[0x0e]	35119	1			T5	328		T6	2		T7	2
valid_sources[0x0f]	35757	1			T5	305		T6	7		T7	5
valid_sources[0x10]	35779	1			T5	323		T7	1		T12	835
valid_sources[0x11]	35287	1			T5	299		T180	4		T12	816
valid_sources[0x12]	36591	1			T5	276		T6	12		T7	1
valid_sources[0x13]	37198	1			T5	294		T6	6		T7	1
valid_sources[0x14]	36215	1			T5	329		T6	1		T7	3
valid_sources[0x15]	35147	1			T5	320		T6	2		T7	2
valid_sources[0x16]	35886	1			T5	313		T6	8		T7	3
valid_sources[0x17]	34770	1			T5	328		T6	4		T103	2
valid_sources[0x18]	33795	1			T5	309		T6	3		T7	2
valid_sources[0x19]	36246	1			T1	1		T5	332		T6	2
valid_sources[0x1a]	35498	1			T1	1		T5	317		T6	3
valid_sources[0x1b]	35852	1			T5	324		T6	4		T7	2
valid_sources[0x1c]	33787	1			T5	307		T7	3		T108	1
valid_sources[0x1d]	35993	1			T5	303		T6	7		T7	3
valid_sources[0x1e]	34285	1			T5	331		T6	5		T7	2
valid_sources[0x1f]	36959	1			T4	1		T5	332		T6	2
valid_sources[0x20]	35654	1			T5	342		T6	6		T12	796
valid_sources[0x21]	34623	1			T5	339		T6	2		T7	4
valid_sources[0x22]	36811	1			T5	319		T6	5		T7	1
valid_sources[0x23]	35445	1			T5	318		T6	5		T7	2
valid_sources[0x24]	38050	1			T5	310		T7	4		T104	2
valid_sources[0x25]	37828	1			T4	1		T5	280		T6	5
valid_sources[0x26]	35300	1			T5	327		T6	5		T7	2
valid_sources[0x27]	35810	1			T5	314		T6	4		T7	7
valid_sources[0x28]	35839	1			T5	318		T6	4		T7	4
valid_sources[0x29]	36144	1			T5	276		T6	5		T7	1
valid_sources[0x2a]	36110	1			T3	180		T5	321		T6	3
valid_sources[0x2b]	33190	1			T5	339		T6	1		T180	1
valid_sources[0x2c]	34731	1			T5	325		T6	3		T180	1
valid_sources[0x2d]	37422	1			T5	322		T6	10		T7	3
valid_sources[0x2e]	39114	1			T5	342		T6	5		T7	4
valid_sources[0x2f]	36068	1			T5	303		T6	2		T7	2
valid_sources[0x30]	36377	1			T5	357		T6	4		T7	2
valid_sources[0x31]	37393	1			T5	290		T6	7		T7	1
valid_sources[0x32]	34420	1			T5	317		T6	4		T103	9
valid_sources[0x33]	33954	1			T5	315		T8	1		T6	3
valid_sources[0x34]	34598	1			T5	333		T6	4		T7	2
valid_sources[0x35]	33569	1			T5	314		T8	1		T6	4
valid_sources[0x36]	35185	1			T5	322		T6	2		T7	2
valid_sources[0x37]	34898	1			T5	336		T8	1		T6	5
valid_sources[0x38]	36913	1			T5	355		T6	1		T7	2
valid_sources[0x39]	35747	1			T5	314		T6	3		T7	5
valid_sources[0x3a]	34677	1			T5	390		T6	2		T7	3
valid_sources[0x3b]	36814	1			T5	320		T6	6		T103	2
valid_sources[0x3c]	35423	1			T4	1		T5	290		T6	2
valid_sources[0x3d]	34601	1			T5	373		T180	1		T12	847
valid_sources[0x3e]	36087	1			T4	1		T5	316		T6	6
valid_sources[0x3f]	34968	1			T5	307		T6	6		T7	4
valid_sources[0x40]	36247	1			T5	359		T6	1		T7	2
valid_sources[0x41]	35040	1			T5	290		T6	3		T7	2
valid_sources[0x42]	37388	1			T5	350		T6	5		T12	850
valid_sources[0x43]	37472	1			T5	327		T6	7		T7	1
valid_sources[0x44]	35562	1			T5	311		T6	13		T7	2
valid_sources[0x45]	34421	1			T5	297		T6	4		T7	3
valid_sources[0x46]	35580	1			T5	306		T6	18		T7	2
valid_sources[0x47]	34689	1			T5	344		T6	1		T7	1
valid_sources[0x48]	37246	1			T5	328		T6	7		T7	7
valid_sources[0x49]	35573	1			T1	1		T5	290		T6	8
valid_sources[0x4a]	36365	1			T5	340		T8	1		T6	4
valid_sources[0x4b]	34841	1			T5	321		T6	6		T7	1
valid_sources[0x4c]	34663	1			T5	371		T8	2		T6	5
valid_sources[0x4d]	37143	1			T5	319		T6	4		T7	4
valid_sources[0x4e]	34613	1			T5	334		T8	1		T6	2
valid_sources[0x4f]	35899	1			T5	343		T8	1		T6	7
valid_sources[0x50]	35252	1			T5	319		T6	2		T7	1
valid_sources[0x51]	36039	1			T5	324		T6	4		T7	6
valid_sources[0x52]	35031	1			T5	309		T6	2		T7	1
valid_sources[0x53]	37505	1			T5	306		T6	3		T7	3
valid_sources[0x54]	35477	1			T5	356		T6	1		T12	777
valid_sources[0x55]	34547	1			T5	322		T6	7		T7	2
valid_sources[0x56]	34942	1			T5	319		T8	1		T6	4
valid_sources[0x57]	34849	1			T5	330		T6	2		T7	6
valid_sources[0x58]	34878	1			T5	333		T6	8		T7	1
valid_sources[0x59]	35384	1			T5	345		T6	8		T7	5
valid_sources[0x5a]	36476	1			T1	1		T5	353		T6	8
valid_sources[0x5b]	36936	1			T5	326		T6	6		T105	1
valid_sources[0x5c]	34908	1			T5	302		T6	11		T7	5
valid_sources[0x5d]	36634	1			T1	1		T5	314		T6	1
valid_sources[0x5e]	34271	1			T4	1		T5	300		T6	3
valid_sources[0x5f]	37123	1			T5	356		T6	6		T7	2
valid_sources[0x60]	33263	1			T5	322		T6	8		T7	3
valid_sources[0x61]	35369	1			T5	334		T6	2		T7	1
valid_sources[0x62]	34789	1			T5	312		T6	6		T7	5
valid_sources[0x63]	35342	1			T5	310		T6	7		T7	5
valid_sources[0x64]	35517	1			T5	305		T8	1		T6	6
valid_sources[0x65]	36849	1			T5	330		T6	5		T103	2
valid_sources[0x66]	34564	1			T5	349		T6	3		T7	2
valid_sources[0x67]	35977	1			T5	292		T6	6		T7	2
valid_sources[0x68]	36499	1			T5	328		T6	9		T104	1
valid_sources[0x69]	38273	1			T5	294		T6	2		T104	1
valid_sources[0x6a]	36806	1			T4	1		T5	313		T6	4
valid_sources[0x6b]	35990	1			T5	288		T6	1		T7	2
valid_sources[0x6c]	35387	1			T5	315		T103	1		T7	6
valid_sources[0x6d]	35242	1			T5	320		T104	1		T180	1
valid_sources[0x6e]	37861	1			T1	1		T5	340		T7	3
valid_sources[0x6f]	36308	1			T5	313		T6	12		T104	1
valid_sources[0x70]	35743	1			T5	356		T6	5		T7	2
valid_sources[0x71]	35131	1			T5	311		T6	3		T104	2
valid_sources[0x72]	37692	1			T5	283		T7	3		T180	1
valid_sources[0x73]	36693	1			T5	315		T6	12		T7	2
valid_sources[0x74]	36691	1			T5	321		T6	7		T7	2
valid_sources[0x75]	35562	1			T5	278		T6	4		T7	3
valid_sources[0x76]	35451	1			T5	310		T6	3		T7	1
valid_sources[0x77]	34639	1			T4	1		T5	327		T6	5
valid_sources[0x78]	39119	1			T5	313		T8	1		T6	1
valid_sources[0x79]	35223	1			T5	378		T7	1		T104	2
valid_sources[0x7a]	35671	1			T5	352		T6	6		T106	1
valid_sources[0x7b]	35677	1			T5	301		T6	1		T7	4
valid_sources[0x7c]	36443	1			T5	301		T6	2		T7	5
valid_sources[0x7d]	35973	1			T5	307		T7	5		T154	2
valid_sources[0x7e]	35788	1			T5	312		T8	1		T6	1
valid_sources[0x7f]	37131	1			T5	359		T6	1		T7	4
valid_sources[0x80]	35928	1			T1	1		T5	298		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2284374

1

T1

10

T3

90

T4

10

values[0x0]

all_enables

biggest_size

3352312

1

T1

4

T3

42

T4

5

values[0x1]

all_enables

biggest_size

3352320

1

T1

6

T3

48

T4

5