Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25319781

1

T1

1871

T2

385

T3

3114

full_word

8277792

1

T1

440

T2

164

T3

2782

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33597263	1			T1	2311		T2	549		T3	5896
auto[TlIntgErrCmd]	104	1			T257	2		T258	5		T259	4
auto[TlIntgErrData]	101	1			T257	6		T258	7		T259	2
auto[TlIntgErrBoth]	105	1			T257	2		T258	8		T259	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9698107

1

T1

2172

T2

348

T3

5352

auto[1]

23899466

1

T1

139

T2

201

T3

544

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6148115	1			T1	1795		T2	269		T3	2787
auto[TlIntgErrNone]	partial	auto[1]	19171380	1			T1	76		T2	116		T3	327
auto[TlIntgErrNone]	full_word	auto[0]	3549848	1			T1	377		T2	79		T3	2565
auto[TlIntgErrNone]	full_word	auto[1]	4727920	1			T1	63		T2	85		T3	217
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T257	1		T258	1		T259	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T257	1		T258	4		T259	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T352	1		T267	1		T356	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T269	1		T357	1		T358	2
auto[TlIntgErrData]	partial	auto[0]	42	1			T257	1		T258	4		T259	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T257	4		T258	3		T259	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T349	1		T359	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T257	1		T357	2		T358	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T257	1		T258	1		T259	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T257	1		T258	5		T259	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T258	1		T269	1		T355	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T258	1		T354	2		-	-