Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.81	97.40	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	464548591	8104209	0	0
check_regwen_rd_A	464548591	3068	0	0
check_timeout_rd_A	464548591	2372	0	0
check_trigger_regwen_rd_A	464548591	3194	0	0
consistency_check_period_rd_A	464548591	3338	0	0
creator_sw_cfg_read_lock_rd_A	464548591	2282	0	0
direct_access_address_rd_A	464548591	2117	0	0
direct_access_wdata_0_rd_A	464548591	1568	0	0
direct_access_wdata_1_rd_A	464548591	1686	0	0
integrity_check_period_rd_A	464548591	3102	0	0
intr_enable_rd_A	464548591	3928	0	0
owner_sw_cfg_read_lock_rd_A	464548591	2433	0	0
rot_creator_auth_codesign_read_lock_rd_A	464548591	2200	0	0
rot_creator_auth_state_read_lock_rd_A	464548591	2075	0	0
vendor_test_read_lock_rd_A	464548591	2130	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	8104209	0	0
T5	295155	73946	0	0
T6	135661	0	0	0
T7	423612	0	0	0
T8	26181	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T12	0	182409	0	0
T13	0	58161	0	0
T15	0	176491	0	0
T26	0	148898	0	0
T61	16126	0	0	0
T62	13905	0	0	0
T103	25353	0	0	0
T128	0	146675	0	0
T244	0	60912	0	0
T270	0	57730	0	0
T271	0	65921	0	0
T272	0	78069	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	3068	0	0
T18	0	161	0	0
T26	739351	77	0	0
T47	12022	0	0	0
T65	0	196	0	0
T102	128859	0	0	0
T123	0	61	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	55	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	53	0	0
T336	0	57	0	0
T337	0	39	0	0
T338	0	69	0	0
T339	0	148	0	0
T340	42673	0	0	0
T341	56458	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	2372	0	0
T18	0	131	0	0
T26	739351	137	0	0
T47	12022	0	0	0
T65	0	164	0	0
T102	128859	0	0	0
T123	0	48	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	95	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	68	0	0
T336	0	79	0	0
T337	0	77	0	0
T338	0	182	0	0
T339	0	110	0	0
T340	42673	0	0	0
T341	56458	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	3194	0	0
T18	0	138	0	0
T26	739351	64	0	0
T47	12022	0	0	0
T65	0	166	0	0
T102	128859	0	0	0
T123	0	50	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	78	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	36	0	0
T336	0	81	0	0
T337	0	29	0	0
T338	0	113	0	0
T339	0	114	0	0
T340	42673	0	0	0
T341	56458	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	3338	0	0
T18	0	121	0	0
T26	739351	129	0	0
T47	12022	0	0	0
T65	0	148	0	0
T102	128859	0	0	0
T123	0	80	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	68	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	83	0	0
T336	0	46	0	0
T337	0	69	0	0
T338	0	103	0	0
T339	0	131	0	0
T340	42673	0	0	0
T341	56458	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	2282	0	0
T18	0	147	0	0
T26	739351	92	0	0
T47	12022	0	0	0
T65	0	177	0	0
T102	128859	0	0	0
T123	0	58	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	92	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	61	0	0
T336	0	75	0	0
T337	0	105	0	0
T338	0	123	0	0
T339	0	97	0	0
T340	42673	0	0	0
T341	56458	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	2117	0	0
T18	0	162	0	0
T26	739351	77	0	0
T47	12022	0	0	0
T65	0	224	0	0
T102	128859	0	0	0
T123	0	60	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	68	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	49	0	0
T336	0	53	0	0
T337	0	74	0	0
T338	0	115	0	0
T339	0	101	0	0
T340	42673	0	0	0
T341	56458	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	1568	0	0
T18	0	108	0	0
T26	739351	54	0	0
T47	12022	0	0	0
T65	0	163	0	0
T102	128859	0	0	0
T123	0	54	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	40	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	23	0	0
T336	0	43	0	0
T337	0	42	0	0
T338	0	97	0	0
T339	0	97	0	0
T340	42673	0	0	0
T341	56458	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	1686	0	0
T18	0	136	0	0
T26	739351	53	0	0
T47	12022	0	0	0
T65	0	194	0	0
T102	128859	0	0	0
T123	0	39	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	29	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	35	0	0
T336	0	66	0	0
T337	0	41	0	0
T338	0	116	0	0
T339	0	122	0	0
T340	42673	0	0	0
T341	56458	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	3102	0	0
T18	0	151	0	0
T26	739351	100	0	0
T47	12022	0	0	0
T65	0	175	0	0
T102	128859	0	0	0
T123	0	49	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	58	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	48	0	0
T336	0	72	0	0
T337	0	81	0	0
T338	0	126	0	0
T339	0	98	0	0
T340	42673	0	0	0
T341	56458	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	3928	0	0
T6	135661	10	0	0
T7	423612	0	0	0
T9	114020	0	0	0
T10	15635	0	0	0
T11	164313	0	0	0
T18	0	158	0	0
T26	0	93	0	0
T61	16126	0	0	0
T62	13905	0	0	0
T63	11473	0	0	0
T65	0	210	0	0
T103	25353	0	0	0
T104	118924	0	0	0
T123	0	81	0	0
T212	0	4	0	0
T216	0	60	0	0
T249	0	12	0	0
T276	0	77	0	0
T336	0	49	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	2433	0	0
T18	0	121	0	0
T26	739351	78	0	0
T47	12022	0	0	0
T65	0	171	0	0
T102	128859	0	0	0
T123	0	65	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	73	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	52	0	0
T336	0	118	0	0
T337	0	86	0	0
T338	0	135	0	0
T339	0	177	0	0
T340	42673	0	0	0
T341	56458	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	2200	0	0
T18	0	154	0	0
T26	739351	71	0	0
T47	12022	0	0	0
T65	0	208	0	0
T102	128859	0	0	0
T123	0	50	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	63	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	80	0	0
T336	0	72	0	0
T337	0	41	0	0
T338	0	97	0	0
T339	0	115	0	0
T340	42673	0	0	0
T341	56458	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	2075	0	0
T18	0	168	0	0
T26	739351	102	0	0
T47	12022	0	0	0
T65	0	171	0	0
T102	128859	0	0	0
T123	0	44	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	70	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	31	0	0
T336	0	109	0	0
T337	0	68	0	0
T338	0	100	0	0
T339	0	142	0	0
T340	42673	0	0	0
T341	56458	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464548591	2130	0	0
T18	0	118	0	0
T26	739351	121	0	0
T47	12022	0	0	0
T65	0	172	0	0
T102	128859	0	0	0
T123	0	68	0	0
T174	8717	0	0	0
T175	11858	0	0	0
T216	0	77	0	0
T239	5354	0	0	0
T242	15952	0	0	0
T244	287729	0	0	0
T276	0	67	0	0
T336	0	61	0	0
T337	0	52	0	0
T338	0	118	0	0
T339	0	87	0	0
T340	42673	0	0	0
T341	56458	0	0	0