Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : otp_ctrl_dai
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.07 94.33 90.59 83.33 87.10 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp_ctrl_dai 93.73 95.88 95.06 87.72 90.00 100.00



Module Instance : tb.dut.u_otp_ctrl_dai

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.73 95.88 95.06 87.72 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.38 85.64 91.96 100.00 87.72 89.73 87.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.81 97.40 96.15 96.90 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_part_sel_idx 74.55 65.65 89.83 88.89 53.85
u_prim_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : otp_ctrl_dai
Line No.TotalCoveredPercent
TOTAL24723394.33
ALWAYS16933100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18411100.00
ALWAYS18719918592.96
CONT_ASSIGN71811100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
ALWAYS7531111100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN79711100.00
ALWAYS80333100.00
ALWAYS8061414100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
169 1 1
170 1 1
172 1 1
MISSING_ELSE
177 1 1
179 1 1
180 1 1
184 1 1
187 1 1
190 1 1
191 1 1
194 1 1
195 1 1
196 1 1
199 1 1
200 1 1
203 1 1
206 1 1
207 1 1
208 1 1
209 1 1
212 1 1
213 1 1
214 1 1
217 1 1
218 1 1
219 1 1
222 1 1
223 1 1
225 1 1
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
==> MISSING_ELSE
MISSING_ELSE
247 1 1
248 1 1
249 1 1
250 1 1
251 0 1
252 0 1
254 1 1
MISSING_ELSE
263 1 1
264 1 1
265 1 1
266 1 1
267 1 1
MISSING_ELSE
274 1 1
275 1 1
277 1 1
278 1 1
279 1 1
281 1 1
283 1 1
284 1 1
287 1 1
289 1 1
290 1 1
292 1 1
293 1 1
295 1 1
299 1 1
300 1 1
301 1 1
MISSING_ELSE
313 1 1
317 1 1
320 1 1
321 1 1
323 1 1
325 1 1
326 1 1
MISSING_ELSE
329 1 1
330 1 1
331 1 1
341 1 1
345 1 1
347 1 1
348 1 1
350 1 1
351 1 1
353 1 1
354 1 1
357 1 1
358 1 1
MISSING_ELSE
361 1 1
362 1 1
MISSING_ELSE
369 0 1
370 0 1
380 1 1
381 1 1
382 1 1
383 1 1
384 1 1
385 1 1
MISSING_ELSE
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
399 1 1
MISSING_ELSE
410 1 1
411 1 1
420 1 1
423 1 1
424 1 1
426 1 1
428 1 1
429 1 1
MISSING_ELSE
433 1 1
434 1 1
435 1 1
436 1 1
444 1 1
446 1 1
456 1 1
458 1 1
459 0 1
460 0 1
463 1 1
464 1 1
465 1 1
467 1 1
468 1 1
MISSING_ELSE
MISSING_ELSE
476 0 1
477 0 1
487 1 1
489 1 1
495 1 1
496 1 1
497 1 1
498 1 1
499 1 1
MISSING_ELSE
502 1 1
503 1 1
504 1 1
512 1 1
514 1 1
519 1 1
520 1 1
521 1 1
522 1 1
MISSING_ELSE
528 0 1
529 0 1
536 1 1
537 1 1
539 1 1
540 1 1
541 1 1
MISSING_ELSE
549 1 1
550 1 1
553 1 1
556 1 1
557 1 1
559 0 1
561 1 1
562 1 1
MISSING_ELSE
565 1 1
566 1 1
567 1 1
577 1 1
578 1 1
579 1 1
581 1 1
582 0 1
583 0 1
585 1 1
586 1 1
588 1 1
589 0 1
MISSING_ELSE
MISSING_ELSE
600 1 1
601 1 1
603 1 1
605 1 1
606 1 1
607 1 1
608 1 1
==> MISSING_ELSE
611 1 1
612 1 1
MISSING_ELSE
616 1 1
617 1 1
MISSING_ELSE
620 1 1
621 1 1
MISSING_ELSE
630 1 1
631 1 1
632 1 1
633 1 1
634 1 1
==> MISSING_ELSE
641 1 1
642 1 1
643 1 1
644 1 1
645 1 1
MISSING_ELSE
656 1 1
657 1 1
658 1 1
659 1 1
660 1 1
MISSING_ELSE
668 1 1
669 1 1
MISSING_ELSE
684 1 1
685 1 1
686 1 1
687 1 1
688 1 1
MISSING_ELSE
MISSING_ELSE
718 1 1
721 10 10
753 1 1
754 1 1
757 1 1
758 1 1
759 1 1
761 1 1
762 1 1
763 1 1
765 1 1
768 1 1
769 1 1
MISSING_ELSE
796 1 1
797 1 1
803 3 3
806 1 1
807 1 1
808 1 1
809 1 1
811 1 1
812 1 1
815 1 1
816 1 1
817 1 1
818 1 1
819 1 1
820 1 1
821 1 1
823 1 1
MISSING_ELSE


Cond Coverage for Module : otp_ctrl_dai
TotalCoveredPercent
Conditions857790.59
Logical857790.59
Non-Logical00
Event00

 LINE       170
 EXPRESSION (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity)) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))
             --------------------------1-------------------------    -----------------------------------2-----------------------------------
-1--2-StatusTests
01CoveredT5,T6,T11
10CoveredT1,T2,T3
11CoveredT2,T11,T61

 LINE       184
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       184
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       266
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       350
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT5,T6,T11
11CoveredT1,T2,T3

 LINE       350
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------
-1-StatusTests
0CoveredT5,T6,T11
1CoveredT1,T2,T3

 LINE       357
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T11,T104

 LINE       384
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       467
 EXPRESSION (otp_err == MacroWriteBlankError)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T6,T7

 LINE       498
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       540
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T4,T5

 LINE       588
 EXPRESSION (otp_err == MacroEccCorrError)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       603
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T5

 LINE       668
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT9,T21,T22

 LINE       687
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT2,T3,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00111100000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b10001111000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011000000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[8].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T2,T3

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[9].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T7
11CoveredT1,T4,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[10].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   --------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T6,T7

 LINE       761
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------
-1--2-StatusTests
01CoveredT5,T57,T12
10CoveredT1,T2,T4
11CoveredT1,T4,T5

 LINE       761
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       765
 EXPRESSION 
 Number  Term
      1  (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && 
      2  (base_sel_q == DaiOffset) && 
      3  ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))
-1--2--3-StatusTests
011CoveredT213,T214,T215
101CoveredT12,T216,T217
110CoveredT1,T2,T3
111CoveredT4,T5,T6

 LINE       765
 SUB-EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest)
                 -----------------------1-----------------------    -----------------------2-----------------------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T4

 LINE       765
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------
-1-StatusTests
0CoveredT5,T57,T12
1CoveredT1,T2,T3

 LINE       765
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       818
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       820
 EXPRESSION (data_sel == DaiData)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

FSM Coverage for Module : otp_ctrl_dai
Summary for FSM :: state_q
TotalCoveredPercent
States 20 20 100.00 (Not included in score)
Transitions 48 42 87.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DescrSt 351 Covered T1,T2,T3
DescrWaitSt 385 Covered T1,T2,T3
DigClrSt 299 Covered T1,T4,T5
DigFinSt 608 Covered T1,T4,T5
DigPadSt 612 Covered T4,T5,T8
DigReadSt 541 Covered T1,T4,T5
DigReadWaitSt 562 Covered T1,T4,T5
DigSt 586 Covered T1,T4,T5
DigWaitSt 645 Covered T1,T4,T5
ErrorSt 251 Covered T2,T3,T5
IdleSt 267 Covered T1,T2,T3
InitOtpSt 238 Covered T1,T2,T3
InitPartSt 254 Covered T1,T2,T3
ReadSt 281 Covered T1,T2,T3
ReadWaitSt 326 Covered T1,T2,T3
ResetSt 231 Covered T1,T2,T3
ScrSt 293 Covered T1,T2,T4
ScrWaitSt 499 Covered T1,T2,T4
WriteSt 295 Covered T1,T2,T4
WriteWaitSt 429 Covered T1,T2,T4


transitionsLine No.CoveredTests
DescrSt->DescrWaitSt 385 Covered T1,T2,T3
DescrSt->ErrorSt 685 Covered T218,T219
DescrWaitSt->ErrorSt 685 Not Covered
DescrWaitSt->IdleSt 397 Covered T1,T2,T3
DigClrSt->DigReadSt 541 Covered T1,T4,T5
DigClrSt->ErrorSt 685 Not Covered
DigFinSt->DigWaitSt 645 Covered T1,T4,T5
DigFinSt->ErrorSt 685 Covered T220,T221
DigPadSt->DigFinSt 634 Covered T4,T5,T8
DigPadSt->ErrorSt 685 Covered T222
DigReadSt->DigReadWaitSt 562 Covered T1,T4,T5
DigReadSt->ErrorSt 685 Covered T223,T214
DigReadSt->IdleSt 565 Covered T5,T6,T11
DigReadWaitSt->DigSt 586 Covered T1,T4,T5
DigReadWaitSt->ErrorSt 582 Covered T224,T225,T226
DigSt->DigFinSt 608 Covered T1,T4,T5
DigSt->DigPadSt 612 Covered T4,T5,T8
DigSt->DigReadSt 621 Covered T1,T4,T5
DigSt->ErrorSt 685 Covered T108,T168,T227
DigWaitSt->ErrorSt 685 Covered T12,T228,T229
DigWaitSt->WriteSt 659 Covered T1,T4,T5
IdleSt->DigClrSt 299 Covered T1,T4,T5
IdleSt->ErrorSt 685 Covered T3,T5,T6
IdleSt->ReadSt 281 Covered T1,T2,T3
IdleSt->ScrSt 293 Covered T1,T2,T4
IdleSt->WriteSt 295 Covered T1,T2,T4
InitOtpSt->ErrorSt 251 Covered T230,T231,T232
InitOtpSt->InitPartSt 254 Covered T1,T2,T3
InitPartSt->ErrorSt 685 Covered T2,T10,T61
InitPartSt->IdleSt 267 Covered T1,T2,T3
ReadSt->ErrorSt 685 Not Covered
ReadSt->IdleSt 329 Covered T3,T5,T6
ReadSt->ReadWaitSt 326 Covered T1,T2,T3
ReadWaitSt->DescrSt 351 Covered T1,T2,T3
ReadWaitSt->ErrorSt 361 Covered T5,T6,T7
ReadWaitSt->IdleSt 353 Covered T1,T2,T4
ResetSt->ErrorSt 685 Covered T7,T70,T71
ResetSt->InitOtpSt 238 Covered T1,T2,T3
ScrSt->ErrorSt 685 Not Covered
ScrSt->IdleSt 502 Covered T4,T5,T6
ScrSt->ScrWaitSt 499 Covered T1,T2,T4
ScrWaitSt->ErrorSt 528 Not Covered
ScrWaitSt->WriteSt 521 Covered T1,T2,T4
WriteSt->ErrorSt 685 Not Covered
WriteSt->IdleSt 434 Covered T5,T6,T7
WriteSt->WriteWaitSt 429 Covered T1,T2,T4
WriteWaitSt->ErrorSt 459 Covered T233,T234
WriteWaitSt->IdleSt 464 Covered T1,T2,T4


Summary for FSM :: error_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 12 8 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
AccessError 330 Covered T3,T4,T5
FsmStateError 370 Covered T2,T3,T5
MacroEccCorrError 358 Covered T5,T11,T104
NoError 172 Covered T1,T2,T3


transitionsLine No.CoveredTests
AccessError->FsmStateError 370 Covered T3,T13,T235
AccessError->MacroEccCorrError 358 Not Covered
AccessError->NoError 172 Covered T4,T5,T6
FsmStateError->AccessError 330 Not Covered
FsmStateError->MacroEccCorrError 358 Not Covered
FsmStateError->NoError 172 Covered T2,T3,T5
MacroEccCorrError->AccessError 330 Not Covered
MacroEccCorrError->FsmStateError 370 Covered T155,T236,T237
MacroEccCorrError->NoError 172 Covered T5,T11,T104
NoError->AccessError 330 Covered T3,T4,T5
NoError->FsmStateError 370 Covered T2,T5,T6
NoError->MacroEccCorrError 358 Covered T5,T11,T104



Branch Coverage for Module : otp_ctrl_dai
Line No.TotalCoveredPercent
Branches 93 81 87.10
TERNARY 184 2 2 100.00
IF 170 2 2 100.00
CASE 225 74 62 83.78
IF 684 3 3 100.00
IF 757 4 4 100.00
IF 803 2 2 100.00
IF 806 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 184 ((state_q == IdleSt)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 170 if (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError})))

Branches:
-1-StatusTests
1 Covered T2,T11,T61
0 Covered T1,T2,T3


LineNo. Expression -1-: 225 case (state_q) -2-: 235 if (init_req_i) -3-: 237 if (otp_gnt_i) -4-: 249 if (otp_rvalid_i) -5-: 250 if ((!(otp_err inside {NoError, MacroEccCorrError}))) -6-: 266 if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})) -7-: 275 if (dai_req_i) -8-: 279 case (dai_cmd_i) -9-: 292 if (otp_ctrl_part_pkg::PartInfo[part_idx].secret) -10-: 313 if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))) -11-: 320 if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity) -12-: 325 if (otp_gnt_i) -13-: 341 if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))) -14-: 345 if (otp_rvalid_i) -15-: 347 if ((otp_err inside {NoError, MacroEccCorrError})) -16-: 350 if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))) -17-: 357 if ((otp_err != NoError)) -18-: 384 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -19-: 396 if (scrmbl_valid_i) -20-: 411 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset))))) -21-: 423 if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity) -22-: 428 if (otp_gnt_i) -23-: 446 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset))))) -24-: 456 if (otp_rvalid_i) -25-: 458 if ((!(otp_err inside {NoError, MacroWriteBlankError}))) -26-: 467 if ((otp_err == MacroWriteBlankError)) -27-: 489 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx])))) -28-: 498 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -29-: 514 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx])))) -30-: 520 if (scrmbl_valid_i) -31-: 540 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -32-: 550 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock)) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock))) -33-: 556 if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity) -34-: 561 if (otp_gnt_i) -35-: 578 if (otp_rvalid_i) -36-: 581 if ((!(otp_err inside {NoError, MacroEccCorrError}))) -37-: 588 if ((otp_err == MacroEccCorrError)) -38-: 603 if ((otp_addr_o == digest_addr_lut[part_idx])) -39-: 605 if ((!cnt[0])) -40-: 607 if (scrmbl_ready_i) -41-: 611 if (scrmbl_ready_i) -42-: 616 if ((!cnt[0])) -43-: 620 if (scrmbl_ready_i) -44-: 633 if (scrmbl_ready_i) -45-: 644 if (scrmbl_ready_i) -46-: 658 if (scrmbl_valid_i) -47-: 668 if ((error_q == NoError))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40--41--42--43--44--45--46--47-StatusTests
ResetSt 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
ResetSt 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitOtpSt - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
InitOtpSt - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitOtpSt - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitPartSt - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitPartSt - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - 1 DaiRead - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - 1 DaiWrite 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
IdleSt - - - - - 1 DaiWrite 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
IdleSt - - - - - 1 DaiDigest - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T4,T5
IdleSt - - - - - 1 default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
IdleSt - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ReadSt - - - - - - - - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T7,T96,T106
ReadSt - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T3,T5,T6
ReadWaitSt - - - - - - - - - - - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - - - - - - - - 1 1 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ReadWaitSt - - - - - - - - - - - 1 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T5,T11,T104
ReadWaitSt - - - - - - - - - - - 1 1 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - - - - - - - - 1 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T5,T6,T7
ReadWaitSt - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
DescrSt - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
DescrSt - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T6,T7,T12
DescrWaitSt - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
DescrWaitSt - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
WriteSt - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteSt - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteSt - - - - - - - - - - - - - - - - - - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteSt - - - - - - - - - - - - - - - - - - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T7,T96,T106
WriteSt - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T5,T6,T7
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - - - - - - - - - - Not Covered
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 1 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T5,T6,T7
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 1 0 0 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
ScrSt - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ScrSt - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - Covered T6,T12,T60
ScrSt - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - Covered T4,T5,T6
ScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - Not Covered
DigClrSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - Covered T1,T4,T5
DigClrSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - Covered T6,T7,T12
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - Covered T1,T4,T5
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - Not Covered
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - 1 - - - - - - - - - - - - - Covered T1,T4,T5
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - 0 - - - - - - - - - - - - - Covered T7,T96,T106
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - Covered T5,T6,T11
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - Not Covered
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 1 - - - - - - - - - - Not Covered
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 0 - - - - - - - - - - Covered T1,T4,T5
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 0 - - - - - - - Not Covered
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 1 - - - - - - Covered T4,T5,T8
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 0 - - - - - - Covered T238
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - 1 - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - 0 - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - 1 - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - 0 - - - - Covered T1,T4,T5
DigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T4,T5,T8
DigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Not Covered
DigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - Covered T1,T4,T5
DigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - Covered T1,T4,T5
DigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - Covered T1,T4,T5
DigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - Covered T1,T4,T5
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T9,T21,T22
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T2,T3,T5
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T9,T21,T22


LineNo. Expression -1-: 684 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err)) -2-: 687 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T2,T3,T5
1 0 Covered T2,T3,T5
0 - Covered T1,T2,T3


LineNo. Expression -1-: 757 if (otp_ctrl_part_pkg::PartInfo[part_idx].secret) -2-: 761 if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))) -3-: 765 if ((((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && (base_sel_q == DaiOffset)) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 1 Covered T4,T5,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 803 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 806 if ((!rst_ni)) -2-: 815 if (data_clr) -3-: 817 if (data_en) -4-: 818 if ((data_sel == ScrmblData)) -5-: 820 if ((data_sel == DaiData))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 1 - Covered T1,T2,T3
0 0 1 0 1 Covered T1,T2,T4
0 0 1 0 0 Covered T1,T2,T3
0 0 0 - - Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl_dai
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 33 33 100.00 33 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 33 33 100.00 33 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckNativeOtpWidth0_A 1147 1147 0 0
CheckNativeOtpWidth1_A 1147 1147 0 0
DaiIdleKnown_A 461541576 460690025 0 0
DaiRdataKnown_A 461541576 460690025 0 0
ErrorKnown_A 461541576 460690025 0 0
InitDoneKnown_A 461541576 460690025 0 0
OtpAddrKnown_A 461541576 460690025 0 0
OtpCmdKnown_A 461541576 460690025 0 0
OtpErrorState_A 461541576 333 0 0
OtpReqKnown_A 461541576 460690025 0 0
OtpSizeKnown_A 461541576 460690025 0 0
OtpWdataKnown_A 461541576 460690025 0 0
PartInitReqKnown_A 461541576 460690025 0 0
PartSelMustBeOnehot_A 461541576 460690025 0 0
ScrmblBlockWidthGe8_A 461541576 460690025 0 0
ScrmblCmdKnown_A 461541576 460690025 0 0
ScrmblDataKnown_A 461541576 460690025 0 0
ScrmblModeKnown_A 461541576 460690025 0 0
ScrmblMtxReqKnown_A 461541576 460690025 0 0
ScrmblSelKnown_A 461541576 460690025 0 0
ScrmblValidKnown_A 461541576 460690025 0 0
gen_part_sel[0].PartEndMax_A 1147 1147 0 0
gen_part_sel[10].PartEndMax_A 1147 1147 0 0
gen_part_sel[1].PartEndMax_A 1147 1147 0 0
gen_part_sel[2].PartEndMax_A 1147 1147 0 0
gen_part_sel[3].PartEndMax_A 1147 1147 0 0
gen_part_sel[4].PartEndMax_A 1147 1147 0 0
gen_part_sel[5].PartEndMax_A 1147 1147 0 0
gen_part_sel[6].PartEndMax_A 1147 1147 0 0
gen_part_sel[7].PartEndMax_A 1147 1147 0 0
gen_part_sel[8].PartEndMax_A 1147 1147 0 0
gen_part_sel[9].PartEndMax_A 1147 1147 0 0
u_state_regs_A 461541576 460690025 0 0


CheckNativeOtpWidth0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

CheckNativeOtpWidth1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

DaiIdleKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

DaiRdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 333 0 0
T5 295155 1 0 0
T6 135661 1 0 0
T7 423612 2 0 0
T8 26181 0 0 0
T9 114020 0 0 0
T10 15635 0 0 0
T11 164313 0 0 0
T60 0 2 0 0
T61 16126 0 0 0
T62 13905 0 0 0
T103 25353 0 0 0
T104 0 4 0 0
T140 0 8 0 0
T145 0 6 0 0
T181 0 1 0 0
T186 0 1 0 0
T206 0 1 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

PartInitReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

PartSelMustBeOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblBlockWidthGe8_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblModeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblMtxReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

gen_part_sel[0].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[10].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[1].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[2].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[3].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[4].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[5].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[6].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[7].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[8].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[9].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai
Line No.TotalCoveredPercent
TOTAL24323395.88
ALWAYS16933100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18411100.00
ALWAYS18719518594.87
CONT_ASSIGN71811100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN72111100.00
ALWAYS7531111100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN79711100.00
ALWAYS80333100.00
ALWAYS8061414100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
169 1 1
170 1 1
172 1 1
MISSING_ELSE
177 1 1
179 1 1
180 1 1
184 1 1
187 1 1
190 1 1
191 1 1
194 1 1
195 1 1
196 1 1
199 1 1
200 1 1
203 1 1
206 1 1
207 1 1
208 1 1
209 1 1
212 1 1
213 1 1
214 1 1
217 1 1
218 1 1
219 1 1
222 1 1
223 1 1
225 1 1
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
==> MISSING_ELSE
MISSING_ELSE
247 1 1
248 1 1
249 1 1
250 1 1
251 excluded
Exclude Annotation: VC_COV_UNR
252 excluded
Exclude Annotation: VC_COV_UNR
254 1 1
MISSING_ELSE
263 1 1
264 1 1
265 1 1
266 1 1
267 1 1
MISSING_ELSE
274 1 1
275 1 1
277 1 1
278 1 1
279 1 1
281 1 1
283 1 1
284 1 1
287 1 1
289 1 1
290 1 1
292 1 1
293 1 1
295 1 1
299 1 1
300 1 1
301 1 1
MISSING_ELSE
313 1 1
317 1 1
320 1 1
321 1 1
323 1 1
325 1 1
326 1 1
MISSING_ELSE
329 1 1
330 1 1
331 1 1
341 1 1
345 1 1
347 1 1
348 1 1
350 1 1
351 1 1
353 1 1
354 1 1
357 1 1
358 1 1
MISSING_ELSE
361 1 1
362 1 1
MISSING_ELSE
369 0 1
370 0 1
380 1 1
381 1 1
382 1 1
383 1 1
384 1 1
385 1 1
MISSING_ELSE
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
399 1 1
MISSING_ELSE
410 1 1
411 1 1
420 1 1
423 1 1
424 1 1
426 1 1
428 1 1
429 1 1
MISSING_ELSE
433 1 1
434 1 1
435 1 1
436 1 1
444 1 1
446 1 1
456 1 1
458 1 1
459 excluded
Exclude Annotation: VC_COV_UNR
460 excluded
Exclude Annotation: VC_COV_UNR
463 1 1
464 1 1
465 1 1
467 1 1
468 1 1
MISSING_ELSE
MISSING_ELSE
476 0 1
477 0 1
487 1 1
489 1 1
495 1 1
496 1 1
497 1 1
498 1 1
499 1 1
MISSING_ELSE
502 1 1
503 1 1
504 1 1
512 1 1
514 1 1
519 1 1
520 1 1
521 1 1
522 1 1
MISSING_ELSE
528 0 1
529 0 1
536 1 1
537 1 1
539 1 1
540 1 1
541 1 1
MISSING_ELSE
549 1 1
550 1 1
553 1 1
556 1 1
557 1 1
559 0 1
561 1 1
562 1 1
MISSING_ELSE
565 1 1
566 1 1
567 1 1
577 1 1
578 1 1
579 1 1
581 1 1
582 0 1
583 0 1
585 1 1
586 1 1
588 1 1
589 0 1
MISSING_ELSE
MISSING_ELSE
600 1 1
601 1 1
603 1 1
605 1 1
606 1 1
607 1 1
608 1 1
==> MISSING_ELSE
611 1 1
612 1 1
MISSING_ELSE
616 1 1
617 1 1
MISSING_ELSE
620 1 1
621 1 1
MISSING_ELSE
630 1 1
631 1 1
632 1 1
633 1 1
634 1 1
==> MISSING_ELSE
641 1 1
642 1 1
643 1 1
644 1 1
645 1 1
MISSING_ELSE
656 1 1
657 1 1
658 1 1
659 1 1
660 1 1
MISSING_ELSE
668 1 1
669 1 1
MISSING_ELSE
684 1 1
685 1 1
686 1 1
687 1 1
688 1 1
MISSING_ELSE
MISSING_ELSE
718 1 1
721 10 10
753 1 1
754 1 1
757 1 1
758 1 1
759 1 1
761 1 1
762 1 1
763 1 1
765 1 1
768 1 1
769 1 1
MISSING_ELSE
796 1 1
797 1 1
803 3 3
806 1 1
807 1 1
808 1 1
809 1 1
811 1 1
812 1 1
815 1 1
816 1 1
817 1 1
818 1 1
819 1 1
820 1 1
821 1 1
823 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_otp_ctrl_dai
TotalCoveredPercent
Conditions817795.06
Logical817795.06
Non-Logical00
Event00

 LINE       170
 EXPRESSION (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity)) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))
             --------------------------1-------------------------    -----------------------------------2-----------------------------------
-1--2-StatusTests
01CoveredT5,T6,T11
10CoveredT1,T2,T3
11CoveredT2,T11,T61

 LINE       184
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       184
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       266
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       350
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT5,T6,T11
11CoveredT1,T2,T3

 LINE       350
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------
-1-StatusTests
0CoveredT5,T6,T11
1CoveredT1,T2,T3

 LINE       357
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T11,T104

 LINE       384
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT1,T2,T3

 LINE       467
 EXPRESSION (otp_err == MacroWriteBlankError)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T6,T7

 LINE       498
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT1,T2,T4

 LINE       540
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT1,T4,T5

 LINE       588
 EXPRESSION (otp_err == MacroEccCorrError)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       603
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T5

 LINE       668
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT9,T21,T22

 LINE       687
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT2,T3,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b00111100000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b10001111000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11001111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011000000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[8].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T2,T3

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[9].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T7
11CoveredT1,T4,T5

 LINE       721
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[10].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   --------------------------------------------2-------------------------------------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR
11CoveredT5,T6,T7

 LINE       761
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------
-1--2-StatusTests
01CoveredT5,T57,T12
10CoveredT1,T2,T4
11CoveredT1,T4,T5

 LINE       761
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       765
 EXPRESSION 
 Number  Term
      1  (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && 
      2  (base_sel_q == DaiOffset) && 
      3  ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))
-1--2--3-StatusTests
011CoveredT213,T214,T215
101CoveredT12,T216,T217
110CoveredT1,T2,T3
111CoveredT4,T5,T6

 LINE       765
 SUB-EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest)
                 -----------------------1-----------------------    -----------------------2-----------------------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T4

 LINE       765
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------
-1-StatusTests
0CoveredT5,T57,T12
1CoveredT1,T2,T3

 LINE       765
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       818
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       820
 EXPRESSION (data_sel == DaiData)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

FSM Coverage for Instance : tb.dut.u_otp_ctrl_dai
Summary for FSM :: state_q
TotalCoveredPercent
States 20 20 100.00 (Not included in score)
Transitions 48 42 87.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DescrSt 351 Covered T1,T2,T3
DescrWaitSt 385 Covered T1,T2,T3
DigClrSt 299 Covered T1,T4,T5
DigFinSt 608 Covered T1,T4,T5
DigPadSt 612 Covered T4,T5,T8
DigReadSt 541 Covered T1,T4,T5
DigReadWaitSt 562 Covered T1,T4,T5
DigSt 586 Covered T1,T4,T5
DigWaitSt 645 Covered T1,T4,T5
ErrorSt 251 Covered T2,T3,T5
IdleSt 267 Covered T1,T2,T3
InitOtpSt 238 Covered T1,T2,T3
InitPartSt 254 Covered T1,T2,T3
ReadSt 281 Covered T1,T2,T3
ReadWaitSt 326 Covered T1,T2,T3
ResetSt 231 Covered T1,T2,T3
ScrSt 293 Covered T1,T2,T4
ScrWaitSt 499 Covered T1,T2,T4
WriteSt 295 Covered T1,T2,T4
WriteWaitSt 429 Covered T1,T2,T4


transitionsLine No.CoveredTests
DescrSt->DescrWaitSt 385 Covered T1,T2,T3
DescrSt->ErrorSt 685 Covered T218,T219
DescrWaitSt->ErrorSt 685 Not Covered
DescrWaitSt->IdleSt 397 Covered T1,T2,T3
DigClrSt->DigReadSt 541 Covered T1,T4,T5
DigClrSt->ErrorSt 685 Not Covered
DigFinSt->DigWaitSt 645 Covered T1,T4,T5
DigFinSt->ErrorSt 685 Covered T220,T221
DigPadSt->DigFinSt 634 Covered T4,T5,T8
DigPadSt->ErrorSt 685 Covered T222
DigReadSt->DigReadWaitSt 562 Covered T1,T4,T5
DigReadSt->ErrorSt 685 Covered T223,T214
DigReadSt->IdleSt 565 Covered T5,T6,T11
DigReadWaitSt->DigSt 586 Covered T1,T4,T5
DigReadWaitSt->ErrorSt 582 Covered T224,T225,T226
DigSt->DigFinSt 608 Covered T1,T4,T5
DigSt->DigPadSt 612 Covered T4,T5,T8
DigSt->DigReadSt 621 Covered T1,T4,T5
DigSt->ErrorSt 685 Covered T108,T168,T227
DigWaitSt->ErrorSt 685 Covered T12,T228,T229
DigWaitSt->WriteSt 659 Covered T1,T4,T5
IdleSt->DigClrSt 299 Covered T1,T4,T5
IdleSt->ErrorSt 685 Covered T3,T5,T6
IdleSt->ReadSt 281 Covered T1,T2,T3
IdleSt->ScrSt 293 Covered T1,T2,T4
IdleSt->WriteSt 295 Covered T1,T2,T4
InitOtpSt->ErrorSt 251 Covered T230,T231,T232
InitOtpSt->InitPartSt 254 Covered T1,T2,T3
InitPartSt->ErrorSt 685 Covered T2,T10,T61
InitPartSt->IdleSt 267 Covered T1,T2,T3
ReadSt->ErrorSt 685 Not Covered
ReadSt->IdleSt 329 Covered T3,T5,T6
ReadSt->ReadWaitSt 326 Covered T1,T2,T3
ReadWaitSt->DescrSt 351 Covered T1,T2,T3
ReadWaitSt->ErrorSt 361 Covered T5,T6,T7
ReadWaitSt->IdleSt 353 Covered T1,T2,T4
ResetSt->ErrorSt 685 Covered T7,T70,T71
ResetSt->InitOtpSt 238 Covered T1,T2,T3
ScrSt->ErrorSt 685 Not Covered
ScrSt->IdleSt 502 Covered T4,T5,T6
ScrSt->ScrWaitSt 499 Covered T1,T2,T4
ScrWaitSt->ErrorSt 528 Not Covered
ScrWaitSt->WriteSt 521 Covered T1,T2,T4
WriteSt->ErrorSt 685 Not Covered
WriteSt->IdleSt 434 Covered T5,T6,T7
WriteSt->WriteWaitSt 429 Covered T1,T2,T4
WriteWaitSt->ErrorSt 459 Covered T233,T234
WriteWaitSt->IdleSt 464 Covered T1,T2,T4


Summary for FSM :: error_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 9 8 88.89
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
AccessError 330 Covered T3,T4,T5
FsmStateError 370 Covered T2,T3,T5
MacroEccCorrError 358 Covered T5,T11,T104
NoError 172 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
AccessError->FsmStateError 370 Covered T3,T13,T235
AccessError->MacroEccCorrError 358 Excluded VC_COV_UNR
AccessError->NoError 172 Covered T4,T5,T6
FsmStateError->AccessError 330 Excluded VC_COV_UNR
FsmStateError->MacroEccCorrError 358 Excluded VC_COV_UNR
FsmStateError->NoError 172 Covered T2,T3,T5
MacroEccCorrError->AccessError 330 Not Covered
MacroEccCorrError->FsmStateError 370 Covered T155,T236,T237
MacroEccCorrError->NoError 172 Covered T5,T11,T104
NoError->AccessError 330 Covered T3,T4,T5
NoError->FsmStateError 370 Covered T2,T5,T6
NoError->MacroEccCorrError 358 Covered T5,T11,T104



Branch Coverage for Instance : tb.dut.u_otp_ctrl_dai
Line No.TotalCoveredPercent
Branches 90 81 90.00
TERNARY 184 2 2 100.00
IF 170 2 2 100.00
CASE 225 71 62 87.32
IF 684 3 3 100.00
IF 757 4 4 100.00
IF 803 2 2 100.00
IF 806 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 184 ((state_q == IdleSt)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 170 if (((!otp_ctrl_part_pkg::PartInfo[part_idx].integrity) && (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError})))

Branches:
-1-StatusTests
1 Covered T2,T11,T61
0 Covered T1,T2,T3


LineNo. Expression -1-: 225 case (state_q) -2-: 235 if (init_req_i) -3-: 237 if (otp_gnt_i) -4-: 249 if (otp_rvalid_i) -5-: 250 if ((!(otp_err inside {NoError, MacroEccCorrError}))) -6-: 266 if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})) -7-: 275 if (dai_req_i) -8-: 279 case (dai_cmd_i) -9-: 292 if (otp_ctrl_part_pkg::PartInfo[part_idx].secret) -10-: 313 if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))) -11-: 320 if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity) -12-: 325 if (otp_gnt_i) -13-: 341 if ((part_sel_valid && (prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))) -14-: 345 if (otp_rvalid_i) -15-: 347 if ((otp_err inside {NoError, MacroEccCorrError})) -16-: 350 if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))) -17-: 357 if ((otp_err != NoError)) -18-: 384 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -19-: 396 if (scrmbl_valid_i) -20-: 411 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset))))) -21-: 423 if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity) -22-: 428 if (otp_gnt_i) -23-: 446 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset))))) -24-: 456 if (otp_rvalid_i) -25-: 458 if ((!(otp_err inside {NoError, MacroWriteBlankError}))) -26-: 467 if ((otp_err == MacroWriteBlankError)) -27-: 489 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx])))) -28-: 498 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -29-: 514 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx])))) -30-: 520 if (scrmbl_valid_i) -31-: 540 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i)) -32-: 550 if (((part_sel_valid && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock)) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock))) -33-: 556 if (otp_ctrl_part_pkg::PartInfo[part_idx].integrity) -34-: 561 if (otp_gnt_i) -35-: 578 if (otp_rvalid_i) -36-: 581 if ((!(otp_err inside {NoError, MacroEccCorrError}))) -37-: 588 if ((otp_err == MacroEccCorrError)) -38-: 603 if ((otp_addr_o == digest_addr_lut[part_idx])) -39-: 605 if ((!cnt[0])) -40-: 607 if (scrmbl_ready_i) -41-: 611 if (scrmbl_ready_i) -42-: 616 if ((!cnt[0])) -43-: 620 if (scrmbl_ready_i) -44-: 633 if (scrmbl_ready_i) -45-: 644 if (scrmbl_ready_i) -46-: 658 if (scrmbl_valid_i) -47-: 668 if ((error_q == NoError))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40--41--42--43--44--45--46--47-StatusTestsExclude Annotation
ResetSt 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Excluded VC_COV_UNR
ResetSt 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitOtpSt - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Excluded VC_COV_UNR
InitOtpSt - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitOtpSt - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitPartSt - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
InitPartSt - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - 1 DaiRead - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - 1 DaiWrite 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
IdleSt - - - - - 1 DaiWrite 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
IdleSt - - - - - 1 DaiDigest - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T4,T5
IdleSt - - - - - 1 default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
IdleSt - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ReadSt - - - - - - - - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T7,T96,T106
ReadSt - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T3,T5,T6
ReadWaitSt - - - - - - - - - - - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - - - - - - - - 1 1 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ReadWaitSt - - - - - - - - - - - 1 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T5,T11,T104
ReadWaitSt - - - - - - - - - - - 1 1 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - - - - - - - - 1 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T5,T6,T7
ReadWaitSt - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
DescrSt - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
DescrSt - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T6,T7,T12
DescrWaitSt - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
DescrWaitSt - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
WriteSt - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteSt - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteSt - - - - - - - - - - - - - - - - - - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteSt - - - - - - - - - - - - - - - - - - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T7,T96,T106
WriteSt - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T5,T6,T7
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - - - - - - - - - - Excluded VC_COV_UNR
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 1 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T5,T6,T7
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 1 0 0 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
WriteWaitSt - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
ScrSt - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ScrSt - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - Covered T6,T12,T60
ScrSt - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - Covered T4,T5,T6
ScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - Covered T1,T2,T4
ScrWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - Not Covered
DigClrSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - Covered T1,T4,T5
DigClrSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - Covered T6,T7,T12
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - Covered T1,T4,T5
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - Not Covered
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - 1 - - - - - - - - - - - - - Covered T1,T4,T5
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - 0 - - - - - - - - - - - - - Covered T7,T96,T106
DigReadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - Covered T5,T6,T11
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - Not Covered
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 1 - - - - - - - - - - Not Covered
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 0 - - - - - - - - - - Covered T1,T4,T5
DigReadWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 0 - - - - - - - Not Covered
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 1 - - - - - - Covered T4,T5,T8
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 - 0 - - - - - - Covered T238
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - 1 - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - 0 - - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - 1 - - - - Covered T1,T4,T5
DigSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - 0 - - - - Covered T1,T4,T5
DigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T4,T5,T8
DigPadSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Not Covered
DigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - Covered T1,T4,T5
DigFinSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - Covered T1,T4,T5
DigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - Covered T1,T4,T5
DigWaitSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - Covered T1,T4,T5
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T9,T21,T22
ErrorSt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T2,T3,T5
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T9,T21,T22


LineNo. Expression -1-: 684 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err)) -2-: 687 if ((state_q != ErrorSt))

Branches:
-1--2-StatusTests
1 1 Covered T2,T3,T5
1 0 Covered T2,T3,T5
0 - Covered T1,T2,T3


LineNo. Expression -1-: 757 if (otp_ctrl_part_pkg::PartInfo[part_idx].secret) -2-: 761 if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))) -3-: 765 if ((((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest || otp_ctrl_part_pkg::PartInfo[part_idx].sw_digest) && (base_sel_q == DaiOffset)) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 1 Covered T4,T5,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 803 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 806 if ((!rst_ni)) -2-: 815 if (data_clr) -3-: 817 if (data_en) -4-: 818 if ((data_sel == ScrmblData)) -5-: 820 if ((data_sel == DaiData))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 1 - Covered T1,T2,T3
0 0 1 0 1 Covered T1,T2,T4
0 0 1 0 0 Covered T1,T2,T3
0 0 0 - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_ctrl_dai
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 33 33 100.00 33 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 33 33 100.00 33 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckNativeOtpWidth0_A 1147 1147 0 0
CheckNativeOtpWidth1_A 1147 1147 0 0
DaiIdleKnown_A 461541576 460690025 0 0
DaiRdataKnown_A 461541576 460690025 0 0
ErrorKnown_A 461541576 460690025 0 0
InitDoneKnown_A 461541576 460690025 0 0
OtpAddrKnown_A 461541576 460690025 0 0
OtpCmdKnown_A 461541576 460690025 0 0
OtpErrorState_A 461541576 333 0 0
OtpReqKnown_A 461541576 460690025 0 0
OtpSizeKnown_A 461541576 460690025 0 0
OtpWdataKnown_A 461541576 460690025 0 0
PartInitReqKnown_A 461541576 460690025 0 0
PartSelMustBeOnehot_A 461541576 460690025 0 0
ScrmblBlockWidthGe8_A 461541576 460690025 0 0
ScrmblCmdKnown_A 461541576 460690025 0 0
ScrmblDataKnown_A 461541576 460690025 0 0
ScrmblModeKnown_A 461541576 460690025 0 0
ScrmblMtxReqKnown_A 461541576 460690025 0 0
ScrmblSelKnown_A 461541576 460690025 0 0
ScrmblValidKnown_A 461541576 460690025 0 0
gen_part_sel[0].PartEndMax_A 1147 1147 0 0
gen_part_sel[10].PartEndMax_A 1147 1147 0 0
gen_part_sel[1].PartEndMax_A 1147 1147 0 0
gen_part_sel[2].PartEndMax_A 1147 1147 0 0
gen_part_sel[3].PartEndMax_A 1147 1147 0 0
gen_part_sel[4].PartEndMax_A 1147 1147 0 0
gen_part_sel[5].PartEndMax_A 1147 1147 0 0
gen_part_sel[6].PartEndMax_A 1147 1147 0 0
gen_part_sel[7].PartEndMax_A 1147 1147 0 0
gen_part_sel[8].PartEndMax_A 1147 1147 0 0
gen_part_sel[9].PartEndMax_A 1147 1147 0 0
u_state_regs_A 461541576 460690025 0 0


CheckNativeOtpWidth0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

CheckNativeOtpWidth1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

DaiIdleKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

DaiRdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 333 0 0
T5 295155 1 0 0
T6 135661 1 0 0
T7 423612 2 0 0
T8 26181 0 0 0
T9 114020 0 0 0
T10 15635 0 0 0
T11 164313 0 0 0
T60 0 2 0 0
T61 16126 0 0 0
T62 13905 0 0 0
T103 25353 0 0 0
T104 0 4 0 0
T140 0 8 0 0
T145 0 6 0 0
T181 0 1 0 0
T186 0 1 0 0
T206 0 1 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

PartInitReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

PartSelMustBeOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblBlockWidthGe8_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblModeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblMtxReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

ScrmblValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

gen_part_sel[0].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[10].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[1].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[2].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[3].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[4].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[5].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[6].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[7].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[8].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_part_sel[9].PartEndMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1147 1147 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461541576 460690025 0 0
T1 16789 16473 0 0
T2 11121 10867 0 0
T3 60702 60532 0 0
T4 10462 10286 0 0
T5 295155 295127 0 0
T6 135661 134756 0 0
T8 26181 25599 0 0
T9 114020 111754 0 0
T10 15635 15369 0 0
T11 164313 163205 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%