SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 542541 | 1 | T2 | 924 | T3 | 1010 | T4 | 1706 | ||||
auto[2] | 542789 | 1 | T2 | 925 | T3 | 1010 | T4 | 1707 | ||||
auto[3] | 542609 | 1 | T2 | 924 | T3 | 1010 | T4 | 1706 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6101 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[2] | 6697 | 1 | T2 | 15 | T3 | 11 | T4 | 24 | ||||
auto[3] | 6102 | 1 | T2 | 14 | T3 | 11 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6009 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[2] | 6661 | 1 | T2 | 15 | T3 | 11 | T4 | 24 | ||||
auto[3] | 6009 | 1 | T2 | 14 | T3 | 11 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 14583 | 1 | T2 | 763 | T3 | 10 | T4 | 188 | ||||
auto[2] | 15386 | 1 | T2 | 763 | T3 | 10 | T4 | 188 | ||||
auto[3] | 14635 | 1 | T2 | 763 | T3 | 10 | T4 | 188 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6156 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[2] | 6729 | 1 | T2 | 15 | T3 | 11 | T4 | 25 | ||||
auto[3] | 6156 | 1 | T2 | 14 | T3 | 11 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6140 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[2] | 6642 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[3] | 6140 | 1 | T2 | 14 | T3 | 11 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6110 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[2] | 6909 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[3] | 6112 | 1 | T2 | 14 | T3 | 11 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6102 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[2] | 6584 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[3] | 6102 | 1 | T2 | 14 | T3 | 11 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | STATUS |
ack_wo_req | 0 | Excluded |
[auto[1]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 6045 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[2] | 6908 | 1 | T2 | 14 | T3 | 11 | T4 | 24 | ||||
auto[3] | 6133 | 1 | T2 | 14 | T3 | 11 | T4 | 24 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |