Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25293300

1

T1

686

T2

244069

T3

11026

full_word

8283349

1

T1

209

T2

66306

T3

6321

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33576359	1			T1	895		T2	310375		T3	17347
auto[TlIntgErrCmd]	103	1			T266	6		T267	6		T268	3
auto[TlIntgErrData]	97	1			T266	9		T267	5		T268	4
auto[TlIntgErrBoth]	90	1			T266	5		T267	9		T268	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9857949

1

T1

668

T2

36436

T3

15975

auto[1]

23718700

1

T1

227

T2

273939

T3

1372

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6243940	1			T1	557		T2	19650		T3	10154
auto[TlIntgErrNone]	partial	auto[1]	19049093	1			T1	129		T2	224419		T3	872
auto[TlIntgErrNone]	full_word	auto[0]	3613877	1			T1	111		T2	16786		T3	5821
auto[TlIntgErrNone]	full_word	auto[1]	4669449	1			T1	98		T2	49520		T3	500
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T266	3		T267	2		T268	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T266	3		T267	3		T268	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T267	1		T383	1		T385	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T276	1		T277	2		T274	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T266	3		T267	1		T268	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T266	5		T267	4		T268	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T266	1		T387	1		T384	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T384	1		T388	1		T389	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T266	2		T267	1		T268	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T266	3		T267	7		T268	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T384	1		T274	1		T271	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T267	1		T390	2		-	-