Module Definition
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Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.49 73.49


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.49 73.49


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_double_lfsr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.49 73.49


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.49 73.49


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_double_lfsr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_lfsr
TotalCoveredPercent
Totals 5 4 80.00
Total Bits 166 122 73.49
Total Bits 0->1 83 61 73.49
Total Bits 1->0 83 61 73.49

Ports 5 4 80.00
Port Bits 166 122 73.49
Port Bits 0->1 83 61 73.49
Port Bits 1->0 83 61 73.49

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[39:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[0] Yes Yes *T5 Yes T5 INPUT
entropy_i[1] No No No INPUT
entropy_i[4:2] Yes Yes T5 Yes T5 INPUT
entropy_i[5] No No No INPUT
entropy_i[7:6] Yes Yes T5 Yes T5 INPUT
entropy_i[8] No No No INPUT
entropy_i[9] Yes Yes *T5 Yes T5 INPUT
entropy_i[10] No No No INPUT
entropy_i[11] Yes Yes *T5 Yes T5 INPUT
entropy_i[12] No No No INPUT
entropy_i[13] Yes Yes *T5 Yes T5 INPUT
entropy_i[16:14] No No No INPUT
entropy_i[19:17] Yes Yes T5 Yes T5 INPUT
entropy_i[20] No No No INPUT
entropy_i[24:21] Yes Yes T5 Yes T5 INPUT
entropy_i[25] No No No INPUT
entropy_i[26] Yes Yes *T5 Yes T5 INPUT
entropy_i[38:27] No No No INPUT
entropy_i[39] Yes Yes T5 Yes T5 INPUT
state_o[39:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr
TotalCoveredPercent
Totals 5 4 80.00
Total Bits 166 122 73.49
Total Bits 0->1 83 61 73.49
Total Bits 1->0 83 61 73.49

Ports 5 4 80.00
Port Bits 166 122 73.49
Port Bits 0->1 83 61 73.49
Port Bits 1->0 83 61 73.49

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[39:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[0] Yes Yes *T5 Yes T5 INPUT
entropy_i[1] No No No INPUT
entropy_i[4:2] Yes Yes T5 Yes T5 INPUT
entropy_i[5] No No No INPUT
entropy_i[7:6] Yes Yes T5 Yes T5 INPUT
entropy_i[8] No No No INPUT
entropy_i[9] Yes Yes *T5 Yes T5 INPUT
entropy_i[10] No No No INPUT
entropy_i[11] Yes Yes *T5 Yes T5 INPUT
entropy_i[12] No No No INPUT
entropy_i[13] Yes Yes *T5 Yes T5 INPUT
entropy_i[16:14] No No No INPUT
entropy_i[19:17] Yes Yes T5 Yes T5 INPUT
entropy_i[20] No No No INPUT
entropy_i[24:21] Yes Yes T5 Yes T5 INPUT
entropy_i[25] No No No INPUT
entropy_i[26] Yes Yes *T5 Yes T5 INPUT
entropy_i[38:27] No No No INPUT
entropy_i[39] Yes Yes T5 Yes T5 INPUT
state_o[39:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr
TotalCoveredPercent
Totals 5 4 80.00
Total Bits 166 122 73.49
Total Bits 0->1 83 61 73.49
Total Bits 1->0 83 61 73.49

Ports 5 4 80.00
Port Bits 166 122 73.49
Port Bits 0->1 83 61 73.49
Port Bits 1->0 83 61 73.49

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[39:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[0] Yes Yes *T5 Yes T5 INPUT
entropy_i[1] No No No INPUT
entropy_i[4:2] Yes Yes T5 Yes T5 INPUT
entropy_i[5] No No No INPUT
entropy_i[7:6] Yes Yes T5 Yes T5 INPUT
entropy_i[8] No No No INPUT
entropy_i[9] Yes Yes *T5 Yes T5 INPUT
entropy_i[10] No No No INPUT
entropy_i[11] Yes Yes *T5 Yes T5 INPUT
entropy_i[12] No No No INPUT
entropy_i[13] Yes Yes *T5 Yes T5 INPUT
entropy_i[16:14] No No No INPUT
entropy_i[19:17] Yes Yes T5 Yes T5 INPUT
entropy_i[20] No No No INPUT
entropy_i[24:21] Yes Yes T5 Yes T5 INPUT
entropy_i[25] No No No INPUT
entropy_i[26] Yes Yes *T5 Yes T5 INPUT
entropy_i[38:27] No No No INPUT
entropy_i[39] Yes Yes T5 Yes T5 INPUT
state_o[39:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%