SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
83.33 | 69.44 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
buf_err_code_cg_wrap[OtpSecret0ErrIdx] | 0.00 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 83.33 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 6 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 6 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
fsm_err | 0 | 1 | 1 | |
check_fail | 0 | 1 | 1 | |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 | |
no_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 114969 | 1 | T2 | 1 | T3 | 1 | T9 | 1 | ||||
check_fail | 3 | 1 | T61 | 1 | T62 | 1 | T63 | 1 | ||||
ecc_uncorr_err | 308 | 1 | T43 | 41 | T36 | 1 | T127 | 59 | ||||
ecc_corr_err | 161 | 1 | T59 | 28 | T57 | 26 | T60 | 81 | ||||
no_err | 146071 | 1 | T1 | 26 | T4 | 191 | T5 | 507 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 114925 | 1 | T2 | 1 | T3 | 1 | T9 | 1 | ||||
check_fail | 4 | 1 | T39 | 1 | T40 | 1 | T41 | 1 | ||||
ecc_uncorr_err | 353 | 1 | T56 | 67 | T66 | 69 | T135 | 1 | ||||
ecc_corr_err | 140 | 1 | T38 | 140 | - | - | - | - | ||||
no_err | 145985 | 1 | T1 | 26 | T4 | 191 | T5 | 507 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 115123 | 1 | T3 | 1 | T9 | 1 | T10 | 1 | ||||
check_fail | 10 | 1 | T32 | 1 | T33 | 1 | T34 | 1 | ||||
ecc_uncorr_err | 174 | 1 | T35 | 1 | T114 | 1 | T48 | 1 | ||||
ecc_corr_err | 97 | 1 | T30 | 67 | T31 | 30 | - | - | ||||
no_err | 146455 | 1 | T1 | 26 | T4 | 191 | T5 | 507 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 115104 | 1 | T2 | 1 | T65 | 421 | T6 | 196 | ||||
check_fail | 37 | 1 | T3 | 1 | T46 | 1 | T47 | 1 | ||||
ecc_uncorr_err | 125 | 1 | T78 | 1 | T79 | 1 | T80 | 1 | ||||
ecc_corr_err | 349 | 1 | T43 | 36 | T44 | 135 | T45 | 19 | ||||
no_err | 146086 | 1 | T1 | 26 | T4 | 191 | T5 | 507 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 115154 | 1 | T103 | 1 | T65 | 421 | T104 | 1 | ||||
check_fail | 19 | 1 | T9 | 1 | T53 | 1 | T54 | 1 | ||||
ecc_uncorr_err | 105 | 1 | T28 | 1 | T58 | 1 | T57 | 28 | ||||
ecc_corr_err | 72 | 1 | T51 | 5 | T52 | 67 | - | - | ||||
no_err | 146268 | 1 | T1 | 26 | T4 | 191 | T5 | 507 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |