SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
85.71 | 80.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx] | 57.14 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
unbuf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx] | 85.71 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
57.14 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 3 | 4 | 57.14 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 3 | 4 | 57.14 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
85.71 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 1 | 6 | 85.71 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 3 | 4 | 57.14 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
ecc_uncorr_err | 0 | 1 | 1 | |
ecc_corr_err | 0 | 1 | 1 | |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 115130 | 1 | T65 | 421 | T6 | 196 | T7 | 266 | ||||
check_fail | 3 | 1 | T75 | 1 | T155 | 1 | T166 | 1 | ||||
access_err | 47250 | 1 | T4 | 18 | T5 | 156 | T13 | 20 | ||||
no_err | 99871 | 1 | T1 | 26 | T4 | 173 | T5 | 351 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 114447 | 1 | T65 | 421 | T6 | 196 | T7 | 266 | ||||
check_fail | 4 | 1 | T75 | 1 | T166 | 1 | T170 | 1 | ||||
access_err | 49091 | 1 | T4 | 31 | T5 | 81 | T13 | 5 | ||||
ecc_uncorr_err | 795 | 1 | T103 | 1 | T104 | 1 | T50 | 9 | ||||
ecc_corr_err | 917 | 1 | T43 | 53 | T163 | 4 | T165 | 12 | ||||
no_err | 97005 | 1 | T1 | 26 | T4 | 160 | T5 | 426 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 114682 | 1 | T10 | 1 | T11 | 1 | T12 | 1 | ||||
check_fail | 4 | 1 | T75 | 1 | T155 | 1 | T166 | 1 | ||||
access_err | 48716 | 1 | T4 | 43 | T5 | 113 | T13 | 46 | ||||
ecc_uncorr_err | 573 | 1 | T2 | 1 | T164 | 1 | T187 | 1 | ||||
ecc_corr_err | 1343 | 1 | T56 | 67 | T66 | 81 | T163 | 1 | ||||
no_err | 96822 | 1 | T1 | 26 | T4 | 148 | T5 | 394 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 114898 | 1 | T10 | 1 | T12 | 1 | T103 | 1 | ||||
check_fail | 4 | 1 | T75 | 1 | T155 | 1 | T166 | 1 | ||||
access_err | 47234 | 1 | T4 | 27 | T5 | 145 | T13 | 38 | ||||
ecc_uncorr_err | 338 | 1 | T188 | 1 | T94 | 1 | T205 | 1 | ||||
ecc_corr_err | 1245 | 1 | T56 | 73 | T66 | 2 | T165 | 15 | ||||
no_err | 98296 | 1 | T1 | 26 | T4 | 164 | T5 | 362 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 114495 | 1 | T103 | 1 | T65 | 421 | T6 | 196 | ||||
check_fail | 5 | 1 | T155 | 1 | T166 | 1 | T171 | 1 | ||||
access_err | 46993 | 1 | T4 | 2 | T5 | 209 | T13 | 21 | ||||
ecc_uncorr_err | 738 | 1 | T10 | 1 | T11 | 1 | T12 | 1 | ||||
ecc_corr_err | 907 | 1 | T50 | 1 | T56 | 39 | T66 | 129 | ||||
no_err | 98754 | 1 | T1 | 26 | T4 | 189 | T5 | 298 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |