Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6653922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6454797

1

T1

249

T2

189

T3

269

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7805701	1			T1	832		T2	455		T3	600
values[0x0]	2033767	1			T1	36		T2	125		T3	177
values[0x1]	3269251	1			T1	37		T2	129		T3	156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4359796	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8748923

1

T1

428

T2

316

T3

431

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	47868	1			T1	3		T2	3		T4	7
valid_sources[0x01]	51483	1			T1	4		T2	1		T10	7
valid_sources[0x02]	44890	1			T1	2		T2	3		T10	5
valid_sources[0x03]	45513	1			T1	8		T2	5		T10	2
valid_sources[0x04]	44596	1			T1	4		T2	2		T4	16
valid_sources[0x05]	45016	1			T1	4		T2	2		T10	6
valid_sources[0x06]	48262	1			T1	3		T4	18		T5	33
valid_sources[0x07]	45497	1			T1	3		T2	3		T4	12
valid_sources[0x08]	49773	1			T1	3		T2	5		T4	27
valid_sources[0x09]	51678	1			T1	3		T2	1		T10	2
valid_sources[0x0a]	51070	1			T1	3		T2	2		T10	2
valid_sources[0x0b]	44445	1			T1	3		T2	1		T10	9
valid_sources[0x0c]	45454	1			T1	6		T2	4		T10	6
valid_sources[0x0d]	47846	1			T1	2		T2	3		T10	7
valid_sources[0x0e]	45322	1			T1	1		T2	6		T10	3
valid_sources[0x0f]	46817	1			T1	4		T2	6		T10	7
valid_sources[0x10]	66929	1			T1	1		T2	1		T4	25
valid_sources[0x11]	46136	1			T2	2		T10	4		T4	18
valid_sources[0x12]	53097	1			T1	1		T2	5		T4	20
valid_sources[0x13]	62841	1			T2	1		T10	6		T4	18
valid_sources[0x14]	52194	1			T1	4		T2	5		T4	25
valid_sources[0x15]	47622	1			T1	4		T2	3		T4	14
valid_sources[0x16]	48789	1			T1	6		T2	4		T3	933
valid_sources[0x17]	44412	1			T1	5		T4	15		T5	39
valid_sources[0x18]	45301	1			T1	5		T4	26		T5	22
valid_sources[0x19]	47988	1			T1	5		T2	2		T4	16
valid_sources[0x1a]	46685	1			T1	8		T2	2		T10	4
valid_sources[0x1b]	48947	1			T1	3		T2	4		T10	13
valid_sources[0x1c]	57336	1			T1	2		T2	2		T4	21
valid_sources[0x1d]	59717	1			T1	3		T2	3		T4	4
valid_sources[0x1e]	54581	1			T2	5		T10	8		T4	33
valid_sources[0x1f]	51028	1			T2	4		T10	13		T4	17
valid_sources[0x20]	44653	1			T1	4		T2	2		T4	6
valid_sources[0x21]	50197	1			T1	3		T2	3		T9	857
valid_sources[0x22]	46379	1			T1	10		T2	2		T10	15
valid_sources[0x23]	47678	1			T1	5		T10	2		T4	22
valid_sources[0x24]	52910	1			T1	3		T2	2		T10	6
valid_sources[0x25]	75592	1			T1	2		T2	3		T4	13
valid_sources[0x26]	44596	1			T1	7		T2	3		T10	3
valid_sources[0x27]	50544	1			T1	4		T2	3		T10	3
valid_sources[0x28]	49802	1			T1	12		T2	2		T10	3
valid_sources[0x29]	46388	1			T1	6		T2	8		T10	2
valid_sources[0x2a]	47206	1			T1	5		T2	2		T4	19
valid_sources[0x2b]	55108	1			T1	1		T2	2		T4	20
valid_sources[0x2c]	45963	1			T1	2		T2	4		T4	19
valid_sources[0x2d]	56340	1			T1	2		T2	5		T4	15
valid_sources[0x2e]	50123	1			T1	3		T2	6		T4	20
valid_sources[0x2f]	47296	1			T1	4		T2	5		T4	5
valid_sources[0x30]	47482	1			T1	6		T2	5		T10	2
valid_sources[0x31]	62898	1			T1	1		T2	2		T4	35
valid_sources[0x32]	58649	1			T1	4		T2	6		T4	30
valid_sources[0x33]	46844	1			T1	4		T2	3		T4	17
valid_sources[0x34]	45531	1			T2	1		T10	8		T4	16
valid_sources[0x35]	46998	1			T2	1		T10	4		T4	28
valid_sources[0x36]	58204	1			T1	5		T2	1		T10	2
valid_sources[0x37]	49153	1			T1	8		T4	22		T5	60
valid_sources[0x38]	50491	1			T1	5		T2	1		T10	1
valid_sources[0x39]	55225	1			T1	2		T2	2		T4	25
valid_sources[0x3a]	46281	1			T1	2		T2	12		T4	23
valid_sources[0x3b]	44904	1			T1	1		T2	2		T10	12
valid_sources[0x3c]	52966	1			T1	2		T2	1		T10	3
valid_sources[0x3d]	44736	1			T1	1		T2	4		T4	12
valid_sources[0x3e]	54418	1			T1	4		T2	1		T4	18
valid_sources[0x3f]	46261	1			T1	6		T2	2		T10	8
valid_sources[0x40]	47282	1			T1	11		T2	1		T4	25
valid_sources[0x41]	45458	1			T2	4		T4	26		T5	19
valid_sources[0x42]	48124	1			T1	2		T2	4		T10	2
valid_sources[0x43]	51104	1			T1	1		T2	3		T10	2
valid_sources[0x44]	45769	1			T1	2		T2	4		T4	22
valid_sources[0x45]	48314	1			T1	6		T2	3		T4	22
valid_sources[0x46]	63292	1			T1	3		T2	2		T4	28
valid_sources[0x47]	47496	1			T1	6		T2	2		T10	4
valid_sources[0x48]	69488	1			T1	5		T2	3		T10	1
valid_sources[0x49]	54125	1			T2	2		T10	2		T4	23
valid_sources[0x4a]	53791	1			T1	3		T2	4		T10	4
valid_sources[0x4b]	47426	1			T1	6		T2	3		T10	1
valid_sources[0x4c]	46044	1			T1	8		T2	1		T4	18
valid_sources[0x4d]	50567	1			T1	2		T2	6		T4	30
valid_sources[0x4e]	49850	1			T1	2		T2	3		T10	1
valid_sources[0x4f]	45777	1			T1	1		T2	3		T4	16
valid_sources[0x50]	54742	1			T1	3		T2	4		T4	35
valid_sources[0x51]	50957	1			T1	3		T2	1		T10	3
valid_sources[0x52]	46021	1			T1	6		T2	4		T4	31
valid_sources[0x53]	46446	1			T1	6		T2	5		T4	6
valid_sources[0x54]	46776	1			T1	3		T4	20		T5	28
valid_sources[0x55]	61932	1			T1	7		T2	3		T4	17
valid_sources[0x56]	45355	1			T1	4		T2	4		T10	1
valid_sources[0x57]	45592	1			T1	2		T2	5		T10	6
valid_sources[0x58]	46548	1			T1	5		T10	2		T4	21
valid_sources[0x59]	46782	1			T1	2		T2	3		T10	1
valid_sources[0x5a]	52521	1			T1	7		T2	1		T10	8
valid_sources[0x5b]	46333	1			T1	1		T2	3		T4	30
valid_sources[0x5c]	46771	1			T1	1		T2	5		T10	16
valid_sources[0x5d]	113074	1			T1	1		T2	3		T4	32
valid_sources[0x5e]	45382	1			T1	1		T2	2		T10	10
valid_sources[0x5f]	45580	1			T2	2		T10	5		T4	30
valid_sources[0x60]	47624	1			T1	1		T2	1		T10	16
valid_sources[0x61]	49633	1			T1	1		T2	4		T4	26
valid_sources[0x62]	70687	1			T1	1		T2	7		T10	1
valid_sources[0x63]	46118	1			T1	7		T2	1		T10	6
valid_sources[0x64]	48533	1			T1	1		T10	5		T4	20
valid_sources[0x65]	45566	1			T4	29		T5	28		T11	2
valid_sources[0x66]	57066	1			T1	1		T2	3		T4	23
valid_sources[0x67]	45085	1			T1	2		T10	9		T4	8
valid_sources[0x68]	46508	1			T2	3		T10	1		T4	23
valid_sources[0x69]	46199	1			T1	4		T2	4		T10	6
valid_sources[0x6a]	47826	1			T1	2		T2	2		T4	29
valid_sources[0x6b]	54052	1			T1	5		T2	6		T4	21
valid_sources[0x6c]	59712	1			T1	1		T2	6		T10	2
valid_sources[0x6d]	49059	1			T1	7		T2	2		T4	13
valid_sources[0x6e]	50610	1			T1	3		T2	1		T10	8
valid_sources[0x6f]	45973	1			T1	3		T2	1		T4	19
valid_sources[0x70]	53090	1			T1	2		T4	41		T5	21
valid_sources[0x71]	64973	1			T2	5		T10	3		T4	23
valid_sources[0x72]	47489	1			T1	4		T4	22		T5	11
valid_sources[0x73]	44765	1			T1	7		T2	2		T10	1
valid_sources[0x74]	47623	1			T1	1		T2	3		T10	16
valid_sources[0x75]	46951	1			T1	6		T4	33		T5	28
valid_sources[0x76]	47210	1			T2	1		T10	9		T4	17
valid_sources[0x77]	50007	1			T1	9		T2	3		T4	33
valid_sources[0x78]	48206	1			T1	5		T2	5		T10	15
valid_sources[0x79]	47901	1			T1	1		T2	1		T4	24
valid_sources[0x7a]	46548	1			T2	7		T4	22		T5	21
valid_sources[0x7b]	46099	1			T1	4		T2	3		T10	12
valid_sources[0x7c]	49400	1			T1	10		T2	3		T10	6
valid_sources[0x7d]	59602	1			T1	2		T2	4		T4	25
valid_sources[0x7e]	46675	1			T1	3		T2	3		T10	2
valid_sources[0x7f]	53998	1			T2	4		T4	22		T5	29
valid_sources[0x80]	48691	1			T1	2		T2	3		T4	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3183004

1

T1

221

T2

92

T3

130

values[0x0]

all_enables

biggest_size

1673440

1

T1

14

T2

61

T3

80

values[0x1]

all_enables

biggest_size

1598353

1

T1

14

T2

36

T3

59

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	216836	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7786601

1

T1

20

T4

160

T5

200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2000538	1			T1	10		T4	80		T5	100
values[0x0]	2915397	1			T1	6		T4	34		T5	49
values[0x1]	3087502	1			T1	4		T4	46		T5	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	79073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7924364

1

T1

20

T4

160

T5

200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30379	1			T65	1		T144	2		T18	2
valid_sources[0x01]	31127	1			T1	1		T4	1		T65	1
valid_sources[0x02]	34203	1			T4	1		T13	8		T65	2
valid_sources[0x03]	30767	1			T1	1		T4	1		T8	177
valid_sources[0x04]	31162	1			T4	2		T13	1		T65	1
valid_sources[0x05]	31380	1			T96	8		T222	2		T66	3
valid_sources[0x06]	30117	1			T4	1		T18	4		T8	154
valid_sources[0x07]	32273	1			T13	1		T96	14		T65	1
valid_sources[0x08]	33408	1			T13	7		T50	1		T66	6
valid_sources[0x09]	30477	1			T222	1		T144	1		T18	1
valid_sources[0x0a]	31178	1			T66	1		T144	1		T8	244
valid_sources[0x0b]	30692	1			T4	2		T152	1		T66	1
valid_sources[0x0c]	31135	1			T152	8		T222	2		T143	1
valid_sources[0x0d]	32407	1			T50	2		T222	3		T67	3
valid_sources[0x0e]	32129	1			T65	2		T6	1		T222	1
valid_sources[0x0f]	30057	1			T65	1		T152	2		T66	1
valid_sources[0x10]	30193	1			T4	1		T152	5		T222	1
valid_sources[0x11]	33185	1			T50	2		T144	2		T18	1
valid_sources[0x12]	33703	1			T65	1		T50	1		T66	4
valid_sources[0x13]	31973	1			T4	1		T65	1		T7	2
valid_sources[0x14]	31647	1			T4	1		T6	1		T50	1
valid_sources[0x15]	31447	1			T4	1		T108	2		T8	233
valid_sources[0x16]	30518	1			T4	2		T65	1		T66	1
valid_sources[0x17]	31245	1			T4	1		T13	2		T96	6
valid_sources[0x18]	30931	1			T4	1		T65	1		T8	165
valid_sources[0x19]	30859	1			T65	1		T50	1		T66	4
valid_sources[0x1a]	32077	1			T4	2		T5	200		T222	2
valid_sources[0x1b]	30426	1			T4	1		T96	14		T67	1
valid_sources[0x1c]	32111	1			T4	1		T50	1		T66	2
valid_sources[0x1d]	31213	1			T4	1		T13	1		T67	2
valid_sources[0x1e]	30314	1			T143	1		T8	165		T14	379
valid_sources[0x1f]	30328	1			T65	1		T18	2		T143	1
valid_sources[0x20]	32550	1			T4	1		T222	1		T66	1
valid_sources[0x21]	32414	1			T65	1		T222	1		T8	198
valid_sources[0x22]	30015	1			T66	9		T67	1		T18	2
valid_sources[0x23]	31827	1			T4	2		T65	2		T143	1
valid_sources[0x24]	31471	1			T4	1		T222	1		T66	1
valid_sources[0x25]	30977	1			T4	2		T13	2		T66	1
valid_sources[0x26]	31028	1			T4	2		T7	1		T66	3
valid_sources[0x27]	30544	1			T4	2		T222	1		T108	2
valid_sources[0x28]	31068	1			T152	1		T222	1		T8	232
valid_sources[0x29]	31927	1			T4	1		T50	1		T66	2
valid_sources[0x2a]	32524	1			T4	1		T97	60		T143	1
valid_sources[0x2b]	31879	1			T65	1		T50	1		T144	3
valid_sources[0x2c]	31117	1			T222	1		T143	1		T8	114
valid_sources[0x2d]	31224	1			T108	1		T8	193		T14	263
valid_sources[0x2e]	29150	1			T96	5		T50	1		T152	17
valid_sources[0x2f]	31295	1			T4	1		T222	4		T18	3
valid_sources[0x30]	31938	1			T67	1		T18	3		T8	282
valid_sources[0x31]	32680	1			T222	3		T67	4		T18	1
valid_sources[0x32]	31231	1			T4	1		T65	1		T8	242
valid_sources[0x33]	30736	1			T7	1		T222	4		T67	1
valid_sources[0x34]	31538	1			T108	1		T8	182		T14	319
valid_sources[0x35]	31396	1			T1	1		T4	2		T66	1
valid_sources[0x36]	31317	1			T13	1		T66	2		T67	1
valid_sources[0x37]	31734	1			T4	1		T65	1		T143	1
valid_sources[0x38]	32073	1			T4	4		T65	1		T18	2
valid_sources[0x39]	29750	1			T50	1		T56	200		T222	4
valid_sources[0x3a]	31498	1			T96	8		T65	2		T6	1
valid_sources[0x3b]	31085	1			T65	1		T67	2		T144	1
valid_sources[0x3c]	30812	1			T66	3		T8	252		T14	354
valid_sources[0x3d]	32098	1			T4	1		T143	1		T109	1
valid_sources[0x3e]	29799	1			T65	3		T6	1		T7	1
valid_sources[0x3f]	31538	1			T4	2		T65	1		T8	154
valid_sources[0x40]	29321	1			T67	1		T8	239		T14	357
valid_sources[0x41]	29755	1			T66	2		T144	2		T8	192
valid_sources[0x42]	33236	1			T4	2		T7	1		T66	3
valid_sources[0x43]	29877	1			T65	1		T144	1		T108	2
valid_sources[0x44]	31167	1			T4	1		T152	5		T222	1
valid_sources[0x45]	30238	1			T4	1		T18	2		T143	2
valid_sources[0x46]	30274	1			T50	1		T107	11		T8	195
valid_sources[0x47]	32501	1			T7	2		T50	1		T152	2
valid_sources[0x48]	32239	1			T4	1		T13	4		T65	1
valid_sources[0x49]	30034	1			T144	1		T18	1		T8	160
valid_sources[0x4a]	31257	1			T4	2		T96	8		T107	2
valid_sources[0x4b]	29645	1			T4	1		T50	1		T18	4
valid_sources[0x4c]	31926	1			T4	1		T222	2		T144	2
valid_sources[0x4d]	31375	1			T65	2		T18	1		T8	213
valid_sources[0x4e]	32487	1			T4	2		T67	3		T8	217
valid_sources[0x4f]	29276	1			T7	1		T67	1		T8	177
valid_sources[0x50]	31899	1			T65	1		T144	2		T8	192
valid_sources[0x51]	33125	1			T4	1		T7	1		T222	1
valid_sources[0x52]	31365	1			T4	1		T65	1		T66	1
valid_sources[0x53]	30262	1			T4	2		T7	1		T222	1
valid_sources[0x54]	31454	1			T4	1		T65	2		T67	1
valid_sources[0x55]	30547	1			T65	4		T50	2		T66	4
valid_sources[0x56]	30990	1			T4	1		T65	1		T66	1
valid_sources[0x57]	31564	1			T13	3		T50	4		T18	3
valid_sources[0x58]	30636	1			T65	3		T143	1		T8	143
valid_sources[0x59]	31128	1			T1	1		T96	5		T8	167
valid_sources[0x5a]	32007	1			T152	14		T8	259		T14	272
valid_sources[0x5b]	32442	1			T1	1		T96	6		T67	1
valid_sources[0x5c]	31061	1			T65	2		T7	1		T50	1
valid_sources[0x5d]	31989	1			T4	1		T152	8		T222	2
valid_sources[0x5e]	30972	1			T1	1		T222	3		T66	2
valid_sources[0x5f]	31072	1			T4	1		T50	1		T222	1
valid_sources[0x60]	32427	1			T4	1		T65	3		T152	18
valid_sources[0x61]	30363	1			T143	1		T8	194		T14	261
valid_sources[0x62]	31615	1			T65	1		T50	1		T8	223
valid_sources[0x63]	30884	1			T1	1		T4	1		T65	1
valid_sources[0x64]	30210	1			T66	3		T108	1		T8	211
valid_sources[0x65]	31272	1			T4	2		T6	1		T8	202
valid_sources[0x66]	29989	1			T4	2		T7	1		T18	1
valid_sources[0x67]	31969	1			T152	7		T222	2		T18	3
valid_sources[0x68]	31335	1			T152	11		T144	1		T8	212
valid_sources[0x69]	31669	1			T65	3		T222	1		T8	202
valid_sources[0x6a]	31031	1			T152	11		T18	2		T8	151
valid_sources[0x6b]	32239	1			T4	2		T144	5		T8	208
valid_sources[0x6c]	30014	1			T65	2		T144	1		T18	1
valid_sources[0x6d]	29451	1			T4	2		T65	1		T66	1
valid_sources[0x6e]	31608	1			T66	2		T67	2		T8	245
valid_sources[0x6f]	30900	1			T13	4		T65	1		T144	2
valid_sources[0x70]	30961	1			T4	2		T222	1		T66	1
valid_sources[0x71]	33154	1			T18	6		T143	1		T8	201
valid_sources[0x72]	30024	1			T222	4		T18	2		T8	158
valid_sources[0x73]	32470	1			T4	1		T222	1		T67	2
valid_sources[0x74]	32005	1			T65	2		T144	1		T18	3
valid_sources[0x75]	29995	1			T4	1		T222	1		T67	4
valid_sources[0x76]	30621	1			T8	239		T14	422		T145	1
valid_sources[0x77]	31188	1			T1	1		T13	24		T65	1
valid_sources[0x78]	31008	1			T4	1		T50	1		T222	1
valid_sources[0x79]	31341	1			T1	1		T144	1		T8	232
valid_sources[0x7a]	33576	1			T1	1		T13	1		T65	1
valid_sources[0x7b]	29839	1			T1	1		T4	1		T222	3
valid_sources[0x7c]	30635	1			T4	1		T66	1		T144	1
valid_sources[0x7d]	31056	1			T4	2		T65	1		T50	1
valid_sources[0x7e]	30498	1			T1	1		T65	2		T50	1
valid_sources[0x7f]	31473	1			T108	1		T8	201		T14	270
valid_sources[0x80]	32918	1			T96	2		T222	2		T144	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1986441

1

T1

10

T4

80

T5

100

values[0x0]

all_enables

biggest_size

2900492

1

T1

6

T4

34

T5

49

values[0x1]

all_enables

biggest_size

2899668

1

T1

4

T4

46

T5

51