Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22202730

1

T1

656

T2

520

T3

664

full_word

7398359

1

T1

249

T2

189

T3

269

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29600779	1			T1	905		T2	709		T3	933
auto[TlIntgErrCmd]	97	1			T255	7		T256	12		T257	6
auto[TlIntgErrData]	114	1			T255	9		T256	6		T257	10
auto[TlIntgErrBoth]	99	1			T255	4		T256	2		T257	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8949715

1

T1

832

T2

455

T3

600

auto[1]

20651374

1

T1

73

T2

254

T3

333

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5651043	1			T1	611		T2	363		T3	470
auto[TlIntgErrNone]	partial	auto[1]	16551402	1			T1	45		T2	157		T3	194
auto[TlIntgErrNone]	full_word	auto[0]	3298529	1			T1	221		T2	92		T3	130
auto[TlIntgErrNone]	full_word	auto[1]	4099805	1			T1	28		T2	97		T3	139
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T256	4		T257	3		T345	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T255	6		T256	7		T257	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T256	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T255	1		T349	1		T351	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T255	6		T256	3		T257	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T255	2		T256	3		T257	6
auto[TlIntgErrData]	full_word	auto[0]	5	1			T255	1		T347	1		T346	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T257	1		T347	1		T346	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T255	1		T256	2		T257	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T255	2		T257	2		T345	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T255	1		T347	1		T352	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T257	1		T348	1		T351	1