Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	94.16	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	418739337	7005395	0	0
check_regwen_rd_A	418739337	3072	0	0
check_timeout_rd_A	418739337	2345	0	0
check_trigger_regwen_rd_A	418739337	2910	0	0
consistency_check_period_rd_A	418739337	3053	0	0
creator_sw_cfg_read_lock_rd_A	418739337	2334	0	0
direct_access_address_rd_A	418739337	1186	0	0
direct_access_wdata_0_rd_A	418739337	781	0	0
direct_access_wdata_1_rd_A	418739337	933	0	0
integrity_check_period_rd_A	418739337	2922	0	0
intr_enable_rd_A	418739337	3656	0	0
owner_sw_cfg_read_lock_rd_A	418739337	2109	0	0
rot_creator_auth_codesign_read_lock_rd_A	418739337	2241	0	0
rot_creator_auth_state_read_lock_rd_A	418739337	2311	0	0
vendor_test_read_lock_rd_A	418739337	2205	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	7005395	0	0
T8	160559	45938	0	0
T14	435380	83462	0	0
T15	0	270692	0	0
T19	0	175428	0	0
T20	0	88956	0	0
T29	0	35902	0	0
T37	0	54587	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T219	0	77079	0	0
T220	0	33614	0	0
T223	357688	0	0	0
T260	0	185544	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	3072	0	0
T14	435380	71	0	0
T16	127748	0	0	0
T37	0	46	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	120	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	51	0	0
T262	0	36	0	0
T324	0	32	0	0
T331	0	56	0	0
T332	0	17	0	0
T333	0	68	0	0
T334	0	127	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2345	0	0
T14	435380	137	0	0
T16	127748	0	0	0
T37	0	47	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	168	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	48	0	0
T262	0	78	0	0
T324	0	21	0	0
T331	0	39	0	0
T332	0	5	0	0
T333	0	53	0	0
T334	0	95	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2910	0	0
T14	435380	48	0	0
T16	127748	0	0	0
T37	0	35	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	162	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	29	0	0
T262	0	62	0	0
T324	0	5	0	0
T331	0	57	0	0
T332	0	21	0	0
T333	0	91	0	0
T334	0	117	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	3053	0	0
T14	435380	152	0	0
T16	127748	0	0	0
T37	0	37	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	160	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	60	0	0
T262	0	69	0	0
T324	0	34	0	0
T331	0	51	0	0
T332	0	34	0	0
T333	0	78	0	0
T334	0	107	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2334	0	0
T14	435380	136	0	0
T16	127748	0	0	0
T37	0	39	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	174	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	51	0	0
T262	0	73	0	0
T324	0	16	0	0
T331	0	42	0	0
T332	0	21	0	0
T333	0	70	0	0
T334	0	85	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	1186	0	0
T14	435380	130	0	0
T16	127748	0	0	0
T37	0	54	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	114	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	55	0	0
T262	0	30	0	0
T324	0	9	0	0
T331	0	33	0	0
T332	0	29	0	0
T333	0	28	0	0
T334	0	104	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	781	0	0
T14	435380	71	0	0
T16	127748	0	0	0
T37	0	21	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	93	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	8	0	0
T262	0	76	0	0
T264	0	56	0	0
T331	0	12	0	0
T332	0	11	0	0
T333	0	41	0	0
T334	0	92	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	933	0	0
T14	435380	77	0	0
T16	127748	0	0	0
T37	0	45	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	96	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	35	0	0
T262	0	88	0	0
T324	0	4	0	0
T331	0	26	0	0
T332	0	6	0	0
T333	0	52	0	0
T334	0	89	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2922	0	0
T14	435380	120	0	0
T16	127748	0	0	0
T37	0	16	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	134	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	57	0	0
T262	0	60	0	0
T324	0	8	0	0
T331	0	29	0	0
T332	0	40	0	0
T333	0	34	0	0
T334	0	135	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	3656	0	0
T14	435380	110	0	0
T16	127748	11	0	0
T37	0	56	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	155	0	0
T98	139981	0	0	0
T102	0	11	0	0
T106	125364	0	0	0
T131	0	23	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T230	0	17	0	0
T233	0	53	0	0
T331	0	35	0	0
T335	0	12	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2109	0	0
T14	435380	110	0	0
T16	127748	0	0	0
T37	0	67	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	119	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	31	0	0
T262	0	35	0	0
T324	0	15	0	0
T331	0	39	0	0
T332	0	9	0	0
T333	0	91	0	0
T334	0	104	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2241	0	0
T14	435380	125	0	0
T16	127748	0	0	0
T37	0	31	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	150	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	29	0	0
T262	0	55	0	0
T324	0	8	0	0
T331	0	40	0	0
T332	0	12	0	0
T333	0	50	0	0
T334	0	120	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2311	0	0
T14	435380	134	0	0
T16	127748	0	0	0
T37	0	33	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	148	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	40	0	0
T262	0	85	0	0
T324	0	18	0	0
T331	0	20	0	0
T332	0	5	0	0
T333	0	59	0	0
T334	0	106	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418739337	2205	0	0
T14	435380	69	0	0
T16	127748	0	0	0
T37	0	59	0	0
T47	15976	0	0	0
T64	91312	0	0	0
T95	0	158	0	0
T98	139981	0	0	0
T106	125364	0	0	0
T145	36441	0	0	0
T146	8760	0	0	0
T161	8872	0	0	0
T223	357688	0	0	0
T233	0	31	0	0
T262	0	62	0	0
T324	0	25	0	0
T331	0	54	0	0
T332	0	25	0	0
T333	0	52	0	0
T334	0	108	0	0