Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	94.16	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	94.16	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T79

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T56,T66,T165

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T75,T155,T166
1	Covered	T75,T155,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T13
1	1	Covered	T2,T3,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T9

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T13

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T13

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T9
ReadWaitSt	252	Covered	T2,T3,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T9,T10
IdleSt->ReadSt	236	Covered	T2,T3,T9
InitSt->ErrorSt	315	Covered	T103,T104,T105
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T164,T187
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T5,T13
ReadSt->ReadWaitSt	252	Covered	T2,T3,T9
ReadWaitSt->ErrorSt	276	Covered	T202,T203,T204
ReadWaitSt->IdleSt	270	Covered	T2,T3,T9
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T5,T13
CheckFailError	317	Covered	T75,T155,T166
FsmStateError	289	Covered	T2,T3,T9
MacroEccCorrError	221	Covered	T10,T12,T56
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T14,T145
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T5,T13
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T75,T155,T166
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T10,T12,T79
MacroEccCorrError->NoError	235	Covered	T56,T66,T165
NoError->AccessError	256	Covered	T4,T5,T13
NoError->CheckFailError	317	Covered	T75,T155,T166
NoError->FsmStateError	289	Covered	T2,T3,T9
NoError->MacroEccCorrError	221	Covered	T10,T12,T56

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T79
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T188,T94,T205
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T16,T102
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T13
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T56,T66,T165
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T202,T203,T204
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T65,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T65,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T75,T155,T166
1	0	Covered	T75,T155,T166
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	415724641	414852436	0	0
DigestKnown_A	415724641	414852436	0	0
DigestOffsetMustBeRepresentable_A	1147	1147	0	0
EccErrorState_A	415724641	12110	0	0
ErrorKnown_A	415724641	414852436	0	0
FsmStateKnown_A	415724641	414852436	0	0
InitDoneKnown_A	415724641	414852436	0	0
InitReadLocksPartition_A	415724641	74442193	0	0
InitWriteLocksPartition_A	415724641	74442193	0	0
OffsetMustBeBlockAligned_A	1147	1147	0	0
OtpAddrKnown_A	415724641	414852436	0	0
OtpCmdKnown_A	415724641	414852436	0	0
OtpErrorState_A	415724641	28	0	0
OtpReqKnown_A	415724641	414852436	0	0
OtpSizeKnown_A	415724641	414852436	0	0
OtpWdataKnown_A	415724641	414852436	0	0
ReadLockPropagation_A	415724641	161893085	0	0
SizeMustBeBlockAligned_A	1147	1147	0	0
TlulGntKnown_A	415724641	414852436	0	0
TlulRdataKnown_A	415724641	414852436	0	0
TlulReadOnReadLock_A	415724641	7744	0	0
TlulRerrorKnown_A	415724641	414852436	0	0
TlulRvalidKnown_A	415724641	414852436	0	0
WriteLockPropagation_A	415724641	2294078	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	415724641	28557833	0	0
u_state_regs_A	415724641	414852436	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	12110	0	0
T36	11343	0	0	0
T75	11825	2211	0	0
T92	84102	0	0	0
T93	14538	0	0	0
T94	13140	0	0	0
T95	708579	0	0	0
T155	0	3255	0	0
T166	0	3791	0	0
T172	0	2853	0	0
T173	16692	0	0	0
T174	9922	0	0	0
T175	92445	0	0	0
T176	13941	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	74442193	0	0
T1	15911	808	0	0
T2	12450	3114	0	0
T3	19608	6108	0	0
T4	111926	1413	0	0
T5	166439	2028	0	0
T9	19310	4866	0	0
T10	9216	4583	0	0
T11	13257	4019	0	0
T12	13559	3632	0	0
T13	98351	2783	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	74442193	0	0
T1	15911	808	0	0
T2	12450	3114	0	0
T3	19608	6108	0	0
T4	111926	1413	0	0
T5	166439	2028	0	0
T9	19310	4866	0	0
T10	9216	4583	0	0
T11	13257	4019	0	0
T12	13559	3632	0	0
T13	98351	2783	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	28	0	0
T35	14325	0	0	0
T53	14291	0	0	0
T80	10867	0	0	0
T94	0	1	0	0
T102	617509	0	0	0
T126	48914	0	0	0
T188	11416	1	0	0
T189	12086	0	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	76796	0	0	0
T211	20744	0	0	0
T212	5318	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	161893085	0	0
T4	111926	24182	0	0
T5	166439	60370	0	0
T6	43148	0	0	0
T7	0	15996	0	0
T11	13257	0	0	0
T12	13559	0	0	0
T13	98351	29103	0	0
T17	0	12644	0	0
T56	0	9284	0	0
T65	91463	83466	0	0
T96	47884	2755	0	0
T97	0	12419	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T107	0	8558	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	7744	0	0
T4	111926	3	0	0
T5	166439	12	0	0
T6	43148	5	0	0
T7	0	13	0	0
T11	13257	0	0	0
T12	13559	0	0	0
T13	98351	6	0	0
T50	0	1	0	0
T56	0	13	0	0
T65	91463	16	0	0
T96	47884	0	0	0
T97	0	1	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T152	0	17	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	2294078	0	0
T5	166439	10102	0	0
T6	43148	0	0	0
T7	24633	0	0	0
T11	13257	0	0	0
T12	13559	0	0	0
T13	98351	0	0	0
T16	0	72861	0	0
T18	0	9140	0	0
T56	0	10206	0	0
T65	91463	0	0	0
T66	0	11899	0	0
T96	47884	0	0	0
T98	0	24473	0	0
T101	0	7997	0	0
T102	0	55635	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T106	0	2767	0	0
T126	0	8168	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	28557833	0	0
T4	111926	98029	0	0
T5	166439	119170	0	0
T6	43148	0	0	0
T11	13257	0	0	0
T12	13559	0	0	0
T13	98351	50859	0	0
T17	0	3637	0	0
T18	0	105569	0	0
T56	0	76090	0	0
T65	91463	3297	0	0
T66	0	114796	0	0
T96	47884	37281	0	0
T97	0	31150	0	0
T103	12433	0	0	0
T104	9537	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T79,T35,T36

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T50,T56,T66

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T155,T166,T171
1	Covered	T155,T166,T171

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T13
1	1	Covered	T2,T3,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T9

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T4,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T9
ReadWaitSt	252	Covered	T2,T3,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T9,T65
IdleSt->ReadSt	236	Covered	T2,T3,T9
InitSt->ErrorSt	315	Covered	T2,T103,T104
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T10,T11,T12
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T5,T13
ReadSt->ReadWaitSt	252	Covered	T2,T3,T9
ReadWaitSt->ErrorSt	276	Covered	T158,T193,T213
ReadWaitSt->IdleSt	270	Covered	T2,T3,T9
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T5,T13
CheckFailError	317	Covered	T155,T166,T171
FsmStateError	289	Covered	T2,T3,T9
MacroEccCorrError	221	Covered	T50,T56,T66
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T14,T16
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T5,T13
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T155,T166,T171
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T50,T79,T35
MacroEccCorrError->NoError	235	Covered	T56,T66,T51
NoError->AccessError	256	Covered	T4,T5,T13
NoError->CheckFailError	317	Covered	T155,T166,T171
NoError->FsmStateError	289	Covered	T2,T3,T9
NoError->MacroEccCorrError	221	Covered	T50,T56,T66

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T79,T35,T36
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T16,T102
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T13
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T50,T56,T66
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T158,T193,T213
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T65,T7,T50
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T65,T7,T50
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T155,T166,T171
1	0	Covered	T155,T166,T171
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	415724641	414852436	0	0
DigestKnown_A	415724641	414852436	0	0
DigestOffsetMustBeRepresentable_A	1147	1147	0	0
EccErrorState_A	415724641	16429	0	0
ErrorKnown_A	415724641	414852436	0	0
FsmStateKnown_A	415724641	414852436	0	0
InitDoneKnown_A	415724641	414852436	0	0
InitReadLocksPartition_A	415724641	74621308	0	0
InitWriteLocksPartition_A	415724641	74621308	0	0
OffsetMustBeBlockAligned_A	1147	1147	0	0
OtpAddrKnown_A	415724641	414852436	0	0
OtpCmdKnown_A	415724641	414852436	0	0
OtpErrorState_A	415724641	39	0	0
OtpReqKnown_A	415724641	414852436	0	0
OtpSizeKnown_A	415724641	414852436	0	0
OtpWdataKnown_A	415724641	414852436	0	0
ReadLockPropagation_A	415724641	167518808	0	0
SizeMustBeBlockAligned_A	1147	1147	0	0
TlulGntKnown_A	415724641	414852436	0	0
TlulRdataKnown_A	415724641	414852436	0	0
TlulReadOnReadLock_A	415724641	7407	0	0
TlulRerrorKnown_A	415724641	414852436	0	0
TlulRvalidKnown_A	415724641	414852436	0	0
WriteLockPropagation_A	415724641	1045486	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	415724641	14383412	0	0
u_state_regs_A	415724641	414852436	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	16429	0	0
T155	13291	3255	0	0
T166	0	3791	0	0
T170	0	3962	0	0
T171	0	2568	0	0
T172	0	2853	0	0
T177	9761	0	0	0
T178	38174	0	0	0
T179	7075	0	0	0
T180	34055	0	0	0
T181	23575	0	0	0
T182	45362	0	0	0
T183	14650	0	0	0
T184	375405	0	0	0
T185	12559	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	74621308	0	0
T1	15911	859	0	0
T2	12450	3148	0	0
T3	19608	6159	0	0
T4	111926	1634	0	0
T5	166439	2368	0	0
T9	19310	4917	0	0
T10	9216	4624	0	0
T11	13257	4043	0	0
T12	13559	3673	0	0
T13	98351	3038	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	74621308	0	0
T1	15911	859	0	0
T2	12450	3148	0	0
T3	19608	6159	0	0
T4	111926	1634	0	0
T5	166439	2368	0	0
T9	19310	4917	0	0
T10	9216	4624	0	0
T11	13257	4043	0	0
T12	13559	3673	0	0
T13	98351	3038	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	39	0	0
T4	111926	0	0	0
T5	166439	0	0	0
T10	9216	1	0	0
T11	13257	1	0	0
T12	13559	1	0	0
T13	98351	0	0	0
T65	91463	0	0	0
T96	47884	0	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T158	0	1	0	0
T159	0	1	0	0
T167	0	1	0	0
T193	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	167518808	0	0
T4	111926	16970	0	0
T5	166439	74867	0	0
T6	43148	34801	0	0
T7	0	10919	0	0
T11	13257	0	0	0
T12	13559	0	0	0
T13	98351	22768	0	0
T56	0	12286	0	0
T65	91463	77091	0	0
T96	47884	2451	0	0
T97	0	9787	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T107	0	8543	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147	1147	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	7407	0	0
T4	111926	1	0	0
T5	166439	17	0	0
T6	43148	3	0	0
T7	0	7	0	0
T11	13257	0	0	0
T12	13559	0	0	0
T13	98351	4	0	0
T50	0	2	0	0
T65	91463	18	0	0
T96	47884	1	0	0
T97	0	2	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T152	0	16	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	1045486	0	0
T4	111926	10041	0	0
T5	166439	34011	0	0
T6	43148	0	0	0
T11	13257	0	0	0
T12	13559	0	0	0
T13	98351	0	0	0
T65	91463	0	0	0
T66	0	11899	0	0
T72	0	23044	0	0
T91	0	69289	0	0
T96	47884	0	0	0
T101	0	4952	0	0
T102	0	1740	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T111	0	2887	0	0
T126	0	4457	0	0
T216	0	8362	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	14383412	0	0
T4	111926	97842	0	0
T5	166439	149881	0	0
T10	9216	3518	0	0
T11	13257	0	0	0
T12	13559	2718	0	0
T13	98351	0	0	0
T16	0	3990	0	0
T17	0	3620	0	0
T64	0	81011	0	0
T65	91463	0	0	0
T66	0	114575	0	0
T96	47884	0	0	0
T103	12433	0	0	0
T104	9537	0	0	0
T109	0	9592	0	0
T144	0	3307	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415724641	414852436	0	0
T1	15911	15668	0	0
T2	12450	12163	0	0
T3	19608	19347	0	0
T4	111926	110835	0	0
T5	166439	165010	0	0
T9	19310	19040	0	0
T10	9216	8988	0	0
T11	13257	12981	0	0
T12	13559	13253	0	0
T13	98351	97030	0	0